URLs

diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index 40f1fb974c6c71ec68520d61910c8d1400ce9273..cebb0bb9c3b362f08d3bd8eb4a576f78e330c50d 100644 (file)
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -2,22 +2,19 @@
 
 * <https://git.openpower.foundation/isa/PowerISA/issues/64> 
   [[ls001/discussion]]
-* <https://libre-soc.org/openpower/sv/>
-* <https://libre-soc.org/openpower/sv/compliancy_levels/>
-* <https://libre-soc.org/openpower/transcendentals/>
-* <https://libre-soc.org/openpower/sv/bitmanip>
 * <https://libre-soc.org/openpower/sv/int_fp_mv>
 * <https://libre-soc.org/openpower/sv/fclass/>
-* <https://libre-soc.org/openpower/sv/av_opcodes/>
 * <https://libre-soc.org/openpower/sv/fcvt/>
 * <https://libre-soc.org/openpower/sv/cr_int_predication/>
-* <https://libre-soc.org/openpower/sv/biginteger/>
 
 This proposal is to extend the Power ISA with an Abstract RISC-Paradigm
 Vectorisation Concept that may be applied to **all and any** suitable
 Scalar instructions, present and future, in the Scalar Power ISA.
-The Vectorisation System is called "Simple-V" and the Prefix Format is
-called "SVP64". **Simple-V is not a Traditional Vector ISA and therefore
+The Vectorisation System is called
+["Simple-V"](https://libre-soc.org/openpower/sv/)
+and the Prefix Format is called
+["SVP64"](https://libre-soc.org/openpower/sv/).
+**Simple-V is not a Traditional Vector ISA and therefore
 does not add Vector opcodes**.
 An ISA Concept similar to Simple-V was originally invented in 1994 by
 Peter Hsu (Architect of the MIPS R8000) but was dropped as MIPS did not
@@ -35,8 +32,13 @@ processors that are competitive in the 3D GPU Audio Visual DSP EDGE IoT
 desktop chromebook netbook smartphone laptop markets, performance-leveraged
 by Simple-V.  Simple-V thus has to
 be accompanied by corresponding **Scalar** instructions that bring the
-**Scalar** Power ISA up-to-date.  These include IEEE754 Transcendentals
-AV cryptographic Biginteger and bitmanipulation operations that ARM
+**Scalar** Power ISA up-to-date.  These include IEEE754 
+[Transcendentals](https://libre-soc.org/openpower/transcendentals/)
+[AV](https://libre-soc.org/openpower/sv/av_opcodes/)
+cryptographic
+[Biginteger](https://libre-soc.org/openpower/sv/biginteger/) and 
+[bitmanipulation](https://libre-soc.org/openpower/sv/bitmanip)
+operations that ARM
 Intel AMD and many other ISAs have been adding over the past 12 years
 and Power ISA has not.
 
@@ -57,7 +59,9 @@ Branch.
 
 Simple-V has been subdivided into levels akin to the Power ISA Compliancy
 Levels.  For now let us call them "SV Compliancy Levels" to differentiate
-the two.  The reason for the SV Compliancy Levels is the same as for the
+the two.  The reason for the
+[SV Compliancy Levels](https://libre-soc.org/openpower/sv/compliancy_levels/)
+is the same as for the
 Power ISA Compliancy Levels (SFFS, SFS): to not overburden implementors
 with features that they do not need.  *There is no dependence between
 the two types of Compliancy Levels*. The resources below therefore are
@@ -72,6 +76,8 @@ a feature, allows the same instructions to mean different things on
 different implementations (a different Vector bitwidth).  This means
 that binary interoperability is not only impossible to achieve but
 Illegal Instruction trap-and-emulate is also out of the question.
+Worse than that a **future** vendor implementation may suddenly render
+**all existing** hardware non-interoperable.
 
 **Simple-V guarantees binary interoperability** by defining fixed
 register file bitwidths and size for all instructions.  This does