+2009-10-16 Michael Eager <eager@eagercon.com>
+
+ * microblaze-linux-tdep.c:
+ microblaze_linux_memory_remove_breakpoint(): Add gdbarch to param,
+ replace frame_pc_unwind with get_frame_address_in_block.
+ * microblaze-tdep.c: Remove MICROBLAZE_REGISTER_SIZE.
+ * microblaze-tdep.h: Add MICROBLAZE_REGISTER_SIZE.
+
2008-10-15 Steven G. Kargl <kargl@gcc.gnu.org>
* amd64fbsd-nat.c (amd64fbsd_supply_pcb): Conditionally compile in
static int
-microblaze_linux_memory_remove_breakpoint (struct bp_target_info *bp_tgt)
+microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
+ struct bp_target_info *bp_tgt)
{
CORE_ADDR addr = bp_tgt->placed_address;
const gdb_byte *bp;
struct gdbarch *gdbarch = get_frame_arch (next_frame);
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
- base = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
- if (bias > 0 && frame_pc_unwind (next_frame) != func)
+ base = frame_unwind_register_unsigned (next_frame, MICROBLAZE_SP_REGNUM);
+ if (bias > 0 && get_frame_address_in_block (next_frame) != func)
/* See below, some signal trampolines increment the stack as their
first instruction, need to compensate for that. */
base -= bias;
#define IS_SAVE_HIDDEN_PTR(op, rd, ra, rb) \
((op == add || op == addik) && ra == MICROBLAZE_FIRST_ARGREG && rb == 0)
-/* All registers are 32 bits. */
-#define MICROBLAZE_REGISTER_SIZE 4
-
/* The registers of the Xilinx microblaze processor. */
static const char *microblaze_register_names[] =
MICROBLAZE_RTLBHI_REGNUM
};
+/* All registers are 32 bits. */
+#define MICROBLAZE_REGISTER_SIZE 4
+
/* MICROBLAZE_BREAKPOINT defines the breakpoint that should be used.
Only used for native debugging. */
#define MICROBLAZE_BREAKPOINT {0xb9, 0xcc, 0x00, 0x60}