2003-01-07 Chris Demetriou <cgd@broadcom.com>

        * mips.h: Fix missing space in comment.
        (INSN_ISA1, INSN_ISA2, INSN_ISA3, INSN_ISA4, INSN_ISA5)
        (INSN_ISA32, INSN_ISA32R2, INSN_ISA64): Shift values right
        by four bits.

diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 7386c5edf7007b0ec85265221a3f858c826ac9d1..e40f05694ed56cded839914ed7abcc930ec466ff 100644 (file)
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,10 @@
+2003-01-07  Chris Demetriou  <cgd@broadcom.com>
+
+       * mips.h: Fix missing space in comment.
+       (INSN_ISA1, INSN_ISA2, INSN_ISA3, INSN_ISA4, INSN_ISA5)
+       (INSN_ISA32, INSN_ISA32R2, INSN_ISA64): Shift values right
+       by four bits.
+
 2003-01-02  Chris Demetriou  <cgd@broadcom.com>
 
        * mips.h: Update copyright years to include 2002 (which had

diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index bcc0fc68039ba2c0f8807c051e2d722a3afccd4f..1f90cfd76360bce71877d872b86de99e583e4a46 100644 (file)
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -373,18 +373,18 @@ struct mips_opcode
 
 /* Masks used to mark instructions to indicate which MIPS ISA level
    they were introduced in.  ISAs, as defined below, are logical
-   ORs of these bits, indicatingthat they support the instructions
+   ORs of these bits, indicating that they support the instructions
    defined at the given level.  */
 
 #define INSN_ISA_MASK            0x00000fff
-#define INSN_ISA1                 0x00000010
-#define INSN_ISA2                 0x00000020
-#define INSN_ISA3                 0x00000040
-#define INSN_ISA4                 0x00000080
-#define INSN_ISA5                 0x00000100
-#define INSN_ISA32                0x00000200
-#define INSN_ISA64                0x00000400
-#define INSN_ISA32R2              0x00000800
+#define INSN_ISA1                 0x00000001
+#define INSN_ISA2                 0x00000002
+#define INSN_ISA3                 0x00000004
+#define INSN_ISA4                 0x00000008
+#define INSN_ISA5                 0x00000010
+#define INSN_ISA32                0x00000020
+#define INSN_ISA64                0x00000040
+#define INSN_ISA32R2              0x00000080
 
 /* Masks used for MIPS-defined ASEs.  */
 #define INSN_ASE_MASK            0x0000f000