sim: mn10300: standardize the arch-specific settings a little

Rename mn10300_sim.h to mn10300-sim.h to match other ports, and move most
of the arch-specific content out of sim-main.h to it.  This isn't a big
win though as we still have to include the header in sim-main.h due to the
igen interface: it hardcodes including sim-main.h in its files.  So until
we can fix that, we have to keep bleeding these settings into the common
codes.

Also take the opportunity to purge a lot of unused headers from these.
The local modules should already include the right headers, so there's
no need to force everyone to pull them in.  A lot of this is a hold over
from the pre-igen days of this port.

diff --git a/sim/mn10300/interp.c b/sim/mn10300/interp.c
index 3ea8079b1fa74142dc058688df0534b6675e21db..8467070addb65820f636719a2d5c6f418a82abac 100644 (file)
--- a/sim/mn10300/interp.c
+++ b/sim/mn10300/interp.c
@@ -14,8 +14,6 @@
 #include <stdlib.h>
 #include <string.h>
 
-#include "bfd.h"
-
 
 struct _state State;
 

diff --git a/sim/mn10300/mn10300-sim.h b/sim/mn10300/mn10300-sim.h
new file mode 100644 (file)
index 0000000..f6e4d85
--- /dev/null
+++ b/sim/mn10300/mn10300-sim.h
@@ -0,0 +1,231 @@
+#ifndef MN10300_SIM_H
+#define MN10300_SIM_H
+
+/* For compatibility, until all functions converted to passing
+   SIM_DESC as an argument */
+extern SIM_DESC simulator;
+
+typedef struct
+{
+  uint32_t low, high;
+} dword;
+typedef uint32_t reg_t;
+
+struct simops 
+{
+  long opcode;
+  long mask;
+  void (*func)();
+  int length;
+  int format;
+  int numops;
+  int operands[16];
+};
+
+/* The current state of the processor; registers, memory, etc.  */
+
+struct _state
+{
+  reg_t regs[32];              /* registers, d0-d3, a0-a3, sp, pc, mdr, psw,
+                                  lir, lar, mdrq, plus some room for processor
+                                  specific regs.  */
+  union
+  {
+    reg_t fs[32]; /* FS0-31 */
+    dword fd[16]; /* FD0,2,...,30 */
+  } fpregs;
+
+  /* All internal state modified by signal_exception() that may need to be
+     rolled back for passing moment-of-exception image back to gdb. */
+  reg_t exc_trigger_regs[32];
+  reg_t exc_suspend_regs[32];
+  int exc_suspended;
+
+#define SIM_CPU_EXCEPTION_TRIGGER(SD,CPU,CIA) mn10300_cpu_exception_trigger(SD,CPU,CIA)
+#define SIM_CPU_EXCEPTION_SUSPEND(SD,CPU,EXC) mn10300_cpu_exception_suspend(SD,CPU,EXC)
+#define SIM_CPU_EXCEPTION_RESUME(SD,CPU,EXC) mn10300_cpu_exception_resume(SD,CPU,EXC)
+};
+
+extern struct _state State;
+
+#define PC     (State.regs[REG_PC])
+#define SP     (State.regs[REG_SP])
+
+#define PSW (State.regs[11])
+#define PSW_Z 0x1
+#define PSW_N 0x2
+#define PSW_C 0x4
+#define PSW_V 0x8
+#define PSW_IE LSBIT (11)
+#define PSW_LM LSMASK (10, 8)
+
+#define EXTRACT_PSW_LM LSEXTRACTED16 (PSW, 10, 8)
+#define INSERT_PSW_LM(l) LSINSERTED16 ((l), 10, 8)
+
+#define REG_D0 0
+#define REG_A0 4
+#define REG_SP 8
+#define REG_PC 9
+#define REG_MDR 10
+#define REG_PSW 11
+#define REG_LIR 12
+#define REG_LAR 13
+#define REG_MDRQ 14
+#define REG_E0 15
+#define REG_SSP 23
+#define REG_MSP 24
+#define REG_USP 25
+#define REG_MCRH 26
+#define REG_MCRL 27
+#define REG_MCVF 28
+
+#define REG_FPCR 29
+
+#define FPCR (State.regs[REG_FPCR])
+
+#define FCC_MASK LSMASK (21, 18)
+#define RM_MASK  LSMASK (17, 16) /* Must always be zero.  */
+#define EC_MASK  LSMASK (14, 10)
+#define EE_MASK  LSMASK ( 9,  5)
+#define EF_MASK  LSMASK ( 4,  0)
+#define FPCR_MASK (FCC_MASK | EC_MASK | EE_MASK | EF_MASK)
+
+#define FCC_L LSBIT (21)
+#define FCC_G LSBIT (20)
+#define FCC_E LSBIT (19)
+#define FCC_U LSBIT (18)
+
+#define EC_V LSBIT (14)
+#define EC_Z LSBIT (13)
+#define EC_O LSBIT (12)
+#define EC_U LSBIT (11)
+#define EC_I LSBIT (10)
+
+#define EE_V LSBIT (9)
+#define EE_Z LSBIT (8)
+#define EE_O LSBIT (7)
+#define EE_U LSBIT (6)
+#define EE_I LSBIT (5)
+
+#define EF_V LSBIT (4)
+#define EF_Z LSBIT (3)
+#define EF_O LSBIT (2)
+#define EF_U LSBIT (1)
+#define EF_I LSBIT (0)
+
+#define PSW_FE LSBIT(20)
+#define FPU_DISABLED !(PSW & PSW_FE)
+
+#define XS2FS(X,S) State.fpregs.fs[((X<<4)|(S))]
+#define AS2FS(A,S) State.fpregs.fs[((A<<2)|(S))]
+#define Xf2FD(X,f) State.fpregs.fd[((X<<3)|(f))]
+
+#define FS2FPU(FS,F) sim_fpu_32to (&(F), (FS))
+#define FD2FPU(FD,F) sim_fpu_232to (&(F), ((FD).high), ((FD).low))
+#define FPU2FS(F,FS) sim_fpu_to32 (&(FS), &(F))
+#define FPU2FD(F,FD) sim_fpu_to232 (&((FD).high), &((FD).low), &(F))
+
+#define FETCH32(a,b,c,d) \
+ ((a)+((b)<<8)+((c)<<16)+((d)<<24))
+
+#define FETCH24(a,b,c) \
+ ((a)+((b)<<8)+((c)<<16))
+
+#define FETCH16(a,b) ((a)+((b)<<8))
+
+#define load_byte(ADDR) \
+sim_core_read_unaligned_1 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))
+
+#define load_half(ADDR) \
+sim_core_read_unaligned_2 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))
+
+#define load_word(ADDR) \
+sim_core_read_unaligned_4 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))
+
+#define load_dword(ADDR) \
+u642dw (sim_core_read_unaligned_8 (STATE_CPU (simulator, 0), \
+                                  PC, read_map, (ADDR)))
+
+static INLINE2 dword
+u642dw (uint64_t dw)
+{
+  dword r;
+
+  r.low = (uint32_t)dw;
+  r.high = (uint32_t)(dw >> 32);
+  return r;
+}
+
+#define store_byte(ADDR, DATA) \
+sim_core_write_unaligned_1 (STATE_CPU (simulator, 0), \
+                           PC, write_map, (ADDR), (DATA))
+
+
+#define store_half(ADDR, DATA) \
+sim_core_write_unaligned_2 (STATE_CPU (simulator, 0), \
+                           PC, write_map, (ADDR), (DATA))
+
+
+#define store_word(ADDR, DATA) \
+sim_core_write_unaligned_4 (STATE_CPU (simulator, 0), \
+                           PC, write_map, (ADDR), (DATA))
+#define store_dword(ADDR, DATA) \
+sim_core_write_unaligned_8 (STATE_CPU (simulator, 0), \
+                           PC, write_map, (ADDR), dw2u64 (DATA))
+
+static INLINE2 uint64_t
+dw2u64 (dword data)
+{
+  return data.low | (((uint64_t)data.high) << 32);
+}
+
+/* Bring data in from the cold */
+
+#define IMEM8(EA) \
+(sim_core_read_aligned_1(STATE_CPU(sd, 0), EA, exec_map, (EA)))
+
+#define IMEM8_IMMED(EA, N) \
+(sim_core_read_aligned_1(STATE_CPU(sd, 0), EA, exec_map, (EA) + (N)))
+
+/* Function declarations.  */
+
+INLINE_SIM_MAIN (void) genericAdd (uint32_t source, uint32_t destReg);
+INLINE_SIM_MAIN (void) genericSub (uint32_t source, uint32_t destReg);
+INLINE_SIM_MAIN (void) genericCmp (uint32_t leftOpnd, uint32_t rightOpnd);
+INLINE_SIM_MAIN (void) genericOr (uint32_t source, uint32_t destReg);
+INLINE_SIM_MAIN (void) genericXor (uint32_t source, uint32_t destReg);
+INLINE_SIM_MAIN (void) genericBtst (uint32_t leftOpnd, uint32_t rightOpnd);
+INLINE_SIM_MAIN (void) do_syscall (SIM_DESC sd);
+void program_interrupt (SIM_DESC sd, sim_cpu *cpu, sim_cia cia, SIM_SIGNAL sig);
+
+void mn10300_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word pc);
+void mn10300_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception);
+void mn10300_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception);
+
+void fpu_disabled_exception     (SIM_DESC, sim_cpu *, address_word);
+void fpu_unimp_exception        (SIM_DESC, sim_cpu *, address_word);
+void fpu_check_signal_exception (SIM_DESC, sim_cpu *, address_word);
+
+extern const struct fp_prec_t
+{
+  void (* reg2val) (const void *, sim_fpu *);
+  int (*  round)   (sim_fpu *);
+  void (* val2reg) (const sim_fpu *, void *);
+} fp_single_prec, fp_double_prec;
+
+#define FP_SINGLE (&fp_single_prec)
+#define FP_DOUBLE (&fp_double_prec)
+
+void fpu_rsqrt  (SIM_DESC, sim_cpu *, address_word, const void *, void *, const struct fp_prec_t *);
+void fpu_sqrt   (SIM_DESC, sim_cpu *, address_word, const void *, void *, const struct fp_prec_t *);
+void fpu_cmp    (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const struct fp_prec_t *);
+void fpu_add    (SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *);
+void fpu_sub    (SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *);
+void fpu_mul    (SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *);
+void fpu_div    (SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *);
+void fpu_fmadd  (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *);
+void fpu_fmsub  (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *);
+void fpu_fnmadd (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *);
+void fpu_fnmsub (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *);
+
+#endif

diff --git a/sim/mn10300/mn10300_sim.h b/sim/mn10300/mn10300_sim.h
deleted file mode 100644 (file)
index f1ab23f..0000000
--- a/sim/mn10300/mn10300_sim.h
+++ /dev/null
@@ -1,227 +0,0 @@
-#include <stdio.h>
-#include <ctype.h>
-#include "ansidecl.h"
-#include "sim/callback.h"
-#include "opcode/mn10300.h"
-#include <limits.h>
-#include "sim/sim.h"
-#include "bfd.h"
-#include "sim-fpu.h"
-#include "sim-signal.h"
-
-extern SIM_DESC simulator;
-
-typedef struct
-{
-  uint32_t low, high;
-} dword;
-typedef uint32_t reg_t;
-
-struct simops 
-{
-  long opcode;
-  long mask;
-  void (*func)();
-  int length;
-  int format;
-  int numops;
-  int operands[16];
-};
-
-/* The current state of the processor; registers, memory, etc.  */
-
-struct _state
-{
-  reg_t regs[32];              /* registers, d0-d3, a0-a3, sp, pc, mdr, psw,
-                                  lir, lar, mdrq, plus some room for processor
-                                  specific regs.  */
-  union
-  {
-    reg_t fs[32]; /* FS0-31 */
-    dword fd[16]; /* FD0,2,...,30 */
-  } fpregs;
-
-  /* All internal state modified by signal_exception() that may need to be
-     rolled back for passing moment-of-exception image back to gdb. */
-  reg_t exc_trigger_regs[32];
-  reg_t exc_suspend_regs[32];
-  int exc_suspended;
-
-#define SIM_CPU_EXCEPTION_TRIGGER(SD,CPU,CIA) mn10300_cpu_exception_trigger(SD,CPU,CIA)
-#define SIM_CPU_EXCEPTION_SUSPEND(SD,CPU,EXC) mn10300_cpu_exception_suspend(SD,CPU,EXC)
-#define SIM_CPU_EXCEPTION_RESUME(SD,CPU,EXC) mn10300_cpu_exception_resume(SD,CPU,EXC)
-};
-
-extern struct _state State;
-
-#define PC     (State.regs[REG_PC])
-#define SP     (State.regs[REG_SP])
-
-#define PSW (State.regs[11])
-#define PSW_Z 0x1
-#define PSW_N 0x2
-#define PSW_C 0x4
-#define PSW_V 0x8
-#define PSW_IE LSBIT (11)
-#define PSW_LM LSMASK (10, 8)
-
-#define EXTRACT_PSW_LM LSEXTRACTED16 (PSW, 10, 8)
-#define INSERT_PSW_LM(l) LSINSERTED16 ((l), 10, 8)
-
-#define REG_D0 0
-#define REG_A0 4
-#define REG_SP 8
-#define REG_PC 9
-#define REG_MDR 10
-#define REG_PSW 11
-#define REG_LIR 12
-#define REG_LAR 13
-#define REG_MDRQ 14
-#define REG_E0 15
-#define REG_SSP 23
-#define REG_MSP 24
-#define REG_USP 25
-#define REG_MCRH 26
-#define REG_MCRL 27
-#define REG_MCVF 28
-
-#define REG_FPCR 29
-
-#define FPCR (State.regs[REG_FPCR])
-
-#define FCC_MASK LSMASK (21, 18)
-#define RM_MASK  LSMASK (17, 16) /* Must always be zero.  */
-#define EC_MASK  LSMASK (14, 10)
-#define EE_MASK  LSMASK ( 9,  5)
-#define EF_MASK  LSMASK ( 4,  0)
-#define FPCR_MASK (FCC_MASK | EC_MASK | EE_MASK | EF_MASK)
-
-#define FCC_L LSBIT (21)
-#define FCC_G LSBIT (20)
-#define FCC_E LSBIT (19)
-#define FCC_U LSBIT (18)
-
-#define EC_V LSBIT (14)
-#define EC_Z LSBIT (13)
-#define EC_O LSBIT (12)
-#define EC_U LSBIT (11)
-#define EC_I LSBIT (10)
-
-#define EE_V LSBIT (9)
-#define EE_Z LSBIT (8)
-#define EE_O LSBIT (7)
-#define EE_U LSBIT (6)
-#define EE_I LSBIT (5)
-
-#define EF_V LSBIT (4)
-#define EF_Z LSBIT (3)
-#define EF_O LSBIT (2)
-#define EF_U LSBIT (1)
-#define EF_I LSBIT (0)
-
-#define PSW_FE LSBIT(20)
-#define FPU_DISABLED !(PSW & PSW_FE)
-
-#define XS2FS(X,S) State.fpregs.fs[((X<<4)|(S))]
-#define AS2FS(A,S) State.fpregs.fs[((A<<2)|(S))]
-#define Xf2FD(X,f) State.fpregs.fd[((X<<3)|(f))]
-
-#define FS2FPU(FS,F) sim_fpu_32to (&(F), (FS))
-#define FD2FPU(FD,F) sim_fpu_232to (&(F), ((FD).high), ((FD).low))
-#define FPU2FS(F,FS) sim_fpu_to32 (&(FS), &(F))
-#define FPU2FD(F,FD) sim_fpu_to232 (&((FD).high), &((FD).low), &(F))
-
-#define FETCH32(a,b,c,d) \
- ((a)+((b)<<8)+((c)<<16)+((d)<<24))
-
-#define FETCH24(a,b,c) \
- ((a)+((b)<<8)+((c)<<16))
-
-#define FETCH16(a,b) ((a)+((b)<<8))
-
-#define load_byte(ADDR) \
-sim_core_read_unaligned_1 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))
-
-#define load_half(ADDR) \
-sim_core_read_unaligned_2 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))
-
-#define load_word(ADDR) \
-sim_core_read_unaligned_4 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))
-
-#define load_dword(ADDR) \
-u642dw (sim_core_read_unaligned_8 (STATE_CPU (simulator, 0), \
-                                  PC, read_map, (ADDR)))
-
-static INLINE2 dword
-u642dw (uint64_t dw)
-{
-  dword r;
-
-  r.low = (uint32_t)dw;
-  r.high = (uint32_t)(dw >> 32);
-  return r;
-}
-
-#define store_byte(ADDR, DATA) \
-sim_core_write_unaligned_1 (STATE_CPU (simulator, 0), \
-                           PC, write_map, (ADDR), (DATA))
-
-
-#define store_half(ADDR, DATA) \
-sim_core_write_unaligned_2 (STATE_CPU (simulator, 0), \
-                           PC, write_map, (ADDR), (DATA))
-
-
-#define store_word(ADDR, DATA) \
-sim_core_write_unaligned_4 (STATE_CPU (simulator, 0), \
-                           PC, write_map, (ADDR), (DATA))
-#define store_dword(ADDR, DATA) \
-sim_core_write_unaligned_8 (STATE_CPU (simulator, 0), \
-                           PC, write_map, (ADDR), dw2u64 (DATA))
-
-static INLINE2 uint64_t
-dw2u64 (dword data)
-{
-  return data.low | (((uint64_t)data.high) << 32);
-}
-
-/* Function declarations.  */
-
-INLINE_SIM_MAIN (void) genericAdd (uint32_t source, uint32_t destReg);
-INLINE_SIM_MAIN (void) genericSub (uint32_t source, uint32_t destReg);
-INLINE_SIM_MAIN (void) genericCmp (uint32_t leftOpnd, uint32_t rightOpnd);
-INLINE_SIM_MAIN (void) genericOr (uint32_t source, uint32_t destReg);
-INLINE_SIM_MAIN (void) genericXor (uint32_t source, uint32_t destReg);
-INLINE_SIM_MAIN (void) genericBtst (uint32_t leftOpnd, uint32_t rightOpnd);
-INLINE_SIM_MAIN (void) do_syscall (SIM_DESC sd);
-void program_interrupt (SIM_DESC sd, sim_cpu *cpu, sim_cia cia, SIM_SIGNAL sig);
-
-void mn10300_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word pc);
-void mn10300_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception);
-void mn10300_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception);
-
-void fpu_disabled_exception     (SIM_DESC, sim_cpu *, address_word);
-void fpu_unimp_exception        (SIM_DESC, sim_cpu *, address_word);
-void fpu_check_signal_exception (SIM_DESC, sim_cpu *, address_word);
-
-extern const struct fp_prec_t
-{
-  void (* reg2val) (const void *, sim_fpu *);
-  int (*  round)   (sim_fpu *);
-  void (* val2reg) (const sim_fpu *, void *);
-} fp_single_prec, fp_double_prec;
-
-#define FP_SINGLE (&fp_single_prec)
-#define FP_DOUBLE (&fp_double_prec)
-
-void fpu_rsqrt  (SIM_DESC, sim_cpu *, address_word, const void *, void *, const struct fp_prec_t *);
-void fpu_sqrt   (SIM_DESC, sim_cpu *, address_word, const void *, void *, const struct fp_prec_t *);
-void fpu_cmp    (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const struct fp_prec_t *);
-void fpu_add    (SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *);
-void fpu_sub    (SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *);
-void fpu_mul    (SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *);
-void fpu_div    (SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *);
-void fpu_fmadd  (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *);
-void fpu_fmsub  (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *);
-void fpu_fnmadd (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *);
-void fpu_fnmsub (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *);

diff --git a/sim/mn10300/op_utils.c b/sim/mn10300/op_utils.c
index 2fccf2da207fd58ec6af70ac15ac17665501a404..b29b803d8e7f7b648536e9e755e98d9ce2c301af 100644 (file)
--- a/sim/mn10300/op_utils.c
+++ b/sim/mn10300/op_utils.c
@@ -1,10 +1,7 @@
 /* This must come before any other includes.  */
 #include "defs.h"
 
-#include "sim-main.h"
-#include "sim-signal.h"
-#include "sim-syscall.h"
-
+#include <errno.h>
 #include <time.h>
 #ifdef HAVE_UNISTD_H
 #include <unistd.h>
@@ -13,6 +10,11 @@
 #include <sys/stat.h>
 #include <sys/time.h>
 
+#include "sim/callback.h"
+
+#include "sim-main.h"
+#include "sim-signal.h"
+#include "sim-syscall.h"
 
 
 #define REG0(X) ((X) & 0x3)

diff --git a/sim/mn10300/sim-main.h b/sim/mn10300/sim-main.h
index 77a7ba8ea0d4f488014c88cc978c3011a92ddc16..09887b5923798e1162fd28be7323fd7338784a1c 100644 (file)
--- a/sim/mn10300/sim-main.h
+++ b/sim/mn10300/sim-main.h
@@ -26,40 +26,20 @@
 
 #include "sim-basics.h"
 
-#include <signal.h> /* For kill() in insns:do_trap */
-
-#include <errno.h>
-#ifdef HAVE_UNISTD_H
-#include <unistd.h>
-#endif
-
-/* These are generated files.  */
-#include "itable.h"
-#include "idecode.h"
-
 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR)  \
 mn10300_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR))
 
-
 #include "sim-base.h"
 
-#include "mn10300_sim.h"
-
-/* Bring data in from the cold */
-
-#define IMEM8(EA) \
-(sim_core_read_aligned_1(STATE_CPU(sd, 0), EA, exec_map, (EA)))
-
-#define IMEM8_IMMED(EA, N) \
-(sim_core_read_aligned_1(STATE_CPU(sd, 0), EA, exec_map, (EA) + (N)))
-
-/* For compatibility, until all functions converted to passing
-   SIM_DESC as an argument */
-extern SIM_DESC simulator;
+/**
+ * TODO: Move these includes to the igen files that need them.
+ * This requires extending the igen syntax to support header includes.
+ */
+#include "sim-fpu.h"
+#include "sim-signal.h"
 
-/* (re) initialize the simulator */
+#include "mn10300-sim.h"
 
-extern void engine_init(SIM_DESC sd);
 extern SIM_CORE_SIGNAL_FN mn10300_core_signal;
 
 #endif