verilog_backend: dump attributes on SwitchRule.

This appears to be an omission.

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 18c92521f92a52d959e5c17d5a7c3de7ad64d159..6288502a549bd6efd445e5a5cb310f95bbda950b 100644 (file)
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -1494,6 +1494,7 @@ void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw
                return;
        }
 
+       dump_attributes(f, indent, sw->attributes);
        f << stringf("%s" "casez (", indent.c_str());
        dump_sigspec(f, sw->signal);
        f << stringf(")\n");