sdramphy: remove fixed parameters

diff --git a/misoclib/sdramphy/gensdrphy.py b/misoclib/sdramphy/gensdrphy.py
index 01f79e0c44353824f25a7bc720a3418c9d267d51..fbb5bd4eb8ac390c158efc1b5a37f145e7a208e0 100644 (file)
--- a/misoclib/sdramphy/gensdrphy.py
+++ b/misoclib/sdramphy/gensdrphy.py
@@ -29,14 +29,7 @@ from migen.fhdl.specials import *
 from misoclib import lasmicon
 
 class GENSDRPHY(Module):
-       def __init__(self, pads, memtype, nphases, cl):
-               if memtype not in ["SDR"]:
-                       raise NotImplementedError("GENSDRPHY only supports SDR")
-               if cl != 2:
-                       raise NotImplementedError("GENSDRPHY only supports CAS LATENCY 2")
-               if nphases > 1:
-                       raise NotImplementedError("GENSDRPHY only supports Full Rate (nphases=1)")
-
+       def __init__(self, pads):
                a = flen(pads.a)
                ba = flen(pads.ba)
                d = flen(pads.dq)
@@ -44,17 +37,17 @@ class GENSDRPHY(Module):
                self.phy_settings = lasmicon.PhySettings(
                        memtype=memtype,
                        dfi_d=d,
-                       nphases=nphases,
+                       nphases=1,
                        rdphase=0,
                        wrphase=0,
                        rdcmdphase=0,
                        wrcmdphase=0,
-                       cl=cl,
+                       cl=2,
                        read_latency=4,
                        write_latency=0
                )
                
-               self.dfi = Interface(a, ba, nphases*d, nphases)
+               self.dfi = Interface(a, ba, d)
 
                ###
 

diff --git a/misoclib/sdramphy/s6ddrphy.py b/misoclib/sdramphy/s6ddrphy.py
index 7211ca0033e9c812d39dac323d599b4e7a2128b4..bdd9d6be041812f40e3db0fbf3a02cceb69d425c 100644 (file)
--- a/misoclib/sdramphy/s6ddrphy.py
+++ b/misoclib/sdramphy/s6ddrphy.py
@@ -21,16 +21,13 @@ from migen.genlib.record import *
 from misoclib import lasmicon
 
 class S6DDRPHY(Module):
-       def __init__(self, pads, memtype, nphases, cl, rd_bitslip, wr_bitslip, dqs_ddr_alignment):
+       def __init__(self, pads, memtype, rd_bitslip, wr_bitslip, dqs_ddr_alignment):
                if memtype not in ["DDR", "LPDDR", "DDR2"]:
                        raise NotImplementedError("S6DDRPHY only supports DDR, LPDDR and DDR2")
-               if cl != 3:
-                       raise NotImplementedError("S6DDRPHY only supports CAS LATENCY 3")
-               if nphases != 2:
-                       raise NotImplementedError("S6DDRPHY only supports Half Rate (nphases=2)")
                a = flen(pads.a)
                ba = flen(pads.ba)
                d = flen(pads.dq)
+               nphases = 2
 
                self.phy_settings = lasmicon.PhySettings(
                        memtype=memtype,
@@ -40,7 +37,7 @@ class S6DDRPHY(Module):
                        wrphase=1,
                        rdcmdphase=1,
                        wrcmdphase=0,
-                       cl=cl,
+                       cl=3,
                        read_latency=5,
                        write_latency=0
                )

diff --git a/targets/mlabs_video.py b/targets/mlabs_video.py
index 1df776ea93475b9ff32408d2a67fca09ae625dbd..1b7a18069bc01676aae2387a1d00128b0e6e5f6b 100644 (file)
--- a/targets/mlabs_video.py
+++ b/targets/mlabs_video.py
@@ -69,7 +69,7 @@ class MiniSoC(SDRAMSoC):
                        write_time=16
                )
                self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"), memtype="DDR",
-                       nphases=2, cl=3, rd_bitslip=0, wr_bitslip=3, dqs_ddr_alignment="C1")
+                       rd_bitslip=0, wr_bitslip=3, dqs_ddr_alignment="C1")
                self.register_sdram_phy(self.ddrphy.dfi, self.ddrphy.phy_settings, sdram_geom, sdram_timing)
 
                # Wishbone