radeonsi: set better tessellation tunables on gfx9 and gfx10

same as PAL

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4143>

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 04d514e2174c208999609330335e982879d5e323..418048f940215d6d715bdf5f9c6dd35eced74351 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -5670,7 +5670,14 @@ static void si_init_config(struct si_context *sctx)
                si_pm4_set_reg(pm4, R_00B1C0_SPI_SHADER_REQ_CTRL_VS, 0);
        }
 
-       if (sctx->chip_class >= GFX8) {
+       if (sctx->chip_class >= GFX9) {
+               si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION,
+                              S_028B50_ACCUM_ISOLINE(40) |
+                              S_028B50_ACCUM_TRI(30) |
+                              S_028B50_ACCUM_QUAD(24) |
+                              S_028B50_DONUT_SPLIT(24) |
+                              S_028B50_TRAP_SPLIT(6));
+       } else if (sctx->chip_class >= GFX8) {
                unsigned vgt_tess_distribution;
 
                vgt_tess_distribution =