Map to and from this box if -abc9

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 2c75215cbea5e6ff99ffcdf368062f9212635a61..59f6d1863718b0477ca1a59f8ac4e4cc6e2bec75 100644 (file)
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -242,7 +242,7 @@ struct SynthIce40Pass : public ScriptPass
        {
                if (check_label("begin"))
                {
-                       run("read_verilog -lib -D_ABC +/ice40/cells_sim.v");
+                       run("read_verilog -icells -lib -D_ABC +/ice40/cells_sim.v");
                        run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
                        run("proc");
                }
@@ -298,7 +298,7 @@ struct SynthIce40Pass : public ScriptPass
                        if (nocarry)
                                run("techmap");
                        else
-                               run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
+                               run("techmap -map +/techmap.v -map +/ice40/arith_map.v" + std::string(abc == "abc9" ? " -D _ABC" : ""));
                        if (retime || help_mode)
                                run(abc + " -dff", "(only if -retime)");
                        run("ice40_opt");
@@ -342,6 +342,7 @@ struct SynthIce40Pass : public ScriptPass
                                        else
                                                wire_delay = 250;
                                        run(abc + stringf(" -W %d -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", wire_delay, device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
+                                       run("techmap -D NO_LUT -D _ABC -map +/ice40/cells_map.v");
                                }
                                else
                                        run(abc + " -dress -lut 4", "(skip if -noabc)");