radeon/r200: drop dirty state from texture object + pp_txoffset

this is just more code cleanup for old dead code

diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c
index 0366fc0fbe47593b11fe7d587699c3595cf51147..013064d2b3f33b4b115045adda21cd8443ba133a 100644 (file)
--- a/src/mesa/drivers/dri/r200/r200_state_init.c
+++ b/src/mesa/drivers/dri/r200/r200_state_init.c
@@ -553,7 +553,7 @@ static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom)
      /* workaround for old CS mechanism */
      OUT_BATCH(r200->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]);
    } else if (t->image_override)
-     OUT_BATCH(atom->cmd[10]);
+     OUT_BATCH(t->override_offset);
 
    END_BATCH();
 }

diff --git a/src/mesa/drivers/dri/r200/r200_tex.c b/src/mesa/drivers/dri/r200/r200_tex.c
index 5daacb8c95a95b5dc04bbd5034d4329b697ddf7b..19a6cad80bd4f239344c1a1a0365281069d22ca9 100644 (file)
--- a/src/mesa/drivers/dri/r200/r200_tex.c
+++ b/src/mesa/drivers/dri/r200/r200_tex.c
@@ -400,10 +400,6 @@ static void r200TexParameter( GLcontext *ctx, GLenum target,
    default:
       return;
    }
-
-   /* Mark this texobj as dirty (one bit per tex unit)
-    */
-   t->dirty_state = R200_TEX_ALL;
 }
 
 

diff --git a/src/mesa/drivers/dri/r200/r200_texstate.c b/src/mesa/drivers/dri/r200/r200_texstate.c
index eee4475137b08cfb32a880e7e264c8dc3c9399bd..6432068760be8bc65378a7787b585143deec8aa2 100644 (file)
--- a/src/mesa/drivers/dri/r200/r200_texstate.c
+++ b/src/mesa/drivers/dri/r200/r200_texstate.c
@@ -743,7 +743,8 @@ void r200SetTexOffset(__DRIcontext * pDRICtx, GLint texname,
        if (!offset)
                return;
 
-       t->pp_txoffset = offset;
+       t->bo = NULL;
+       t->override_offset = offset;
        t->pp_txpitch = pitch - 32;
 
        switch (depth) {
@@ -1003,18 +1004,9 @@ static void import_tex_obj_state( r200ContextPtr rmesa,
    cmd[TEX_PP_TXSIZE] = texobj->pp_txsize; /* NPOT only! */
    cmd[TEX_PP_TXPITCH] = texobj->pp_txpitch; /* NPOT only! */
    cmd[TEX_PP_BORDER_COLOR] = texobj->pp_border_color;
-   if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
-      cmd[TEX_PP_TXOFFSET_NEWDRM] = texobj->pp_txoffset;
-   }
-   else {
-      cmd[TEX_PP_TXOFFSET_OLDDRM] = texobj->pp_txoffset;
-   }
 
    if (texobj->base.Target == GL_TEXTURE_CUBE_MAP) {
       GLuint *cube_cmd = &rmesa->hw.cube[unit].cmd[CUBE_CMD_0];
-      //      GLuint bytesPerFace = texobj->base.totalSize / 6;
-      //      ASSERT(texobj->base.totalSize % 6 == 0);
-      GLuint bytesPerFace = 1; // TODO
 
       R200_STATECHANGE( rmesa, cube[unit] );
       cube_cmd[CUBE_PP_CUBIC_FACES] = texobj->pp_cubic_faces;
@@ -1023,14 +1015,8 @@ static void import_tex_obj_state( r200ContextPtr rmesa,
            to not include that command when new drm is used */
         cmd[TEX_PP_CUBIC_FACES] = texobj->pp_cubic_faces;
       }
-      cube_cmd[CUBE_PP_CUBIC_OFFSET_F1] = texobj->pp_txoffset + 1 * bytesPerFace;
-      cube_cmd[CUBE_PP_CUBIC_OFFSET_F2] = texobj->pp_txoffset + 2 * bytesPerFace;
-      cube_cmd[CUBE_PP_CUBIC_OFFSET_F3] = texobj->pp_txoffset + 3 * bytesPerFace;
-      cube_cmd[CUBE_PP_CUBIC_OFFSET_F4] = texobj->pp_txoffset + 4 * bytesPerFace;
-      cube_cmd[CUBE_PP_CUBIC_OFFSET_F5] = texobj->pp_txoffset + 5 * bytesPerFace;
    }
 
-   texobj->dirty_state &= ~(1<<unit);
 }
 
 static void set_texgen_matrix( r200ContextPtr rmesa, 
@@ -1399,7 +1385,6 @@ static void setup_hardware_state(r200ContextPtr rmesa, radeonTexObj *t)
       t->pp_txformat |= R200_TXFORMAT_NON_POWER2;
    }
 
-   t->dirty_state = R200_TEX_ALL;
 }
 
 static GLboolean r200_validate_texture(GLcontext *ctx, struct gl_texture_object *texObj, int unit)
@@ -1429,9 +1414,7 @@ static GLboolean r200_validate_texture(GLcontext *ctx, struct gl_texture_object
    rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_1] |= 4 << (unit * 3);
 
    rmesa->recheck_texgen[unit] = GL_TRUE;
-   if (t->dirty_state & (1<<unit)) {
-      import_tex_obj_state( rmesa, unit, t );
-   }
+   import_tex_obj_state( rmesa, unit, t );
 
    if (rmesa->recheck_texgen[unit]) {
       GLboolean fallback = !r200_validate_texgen( ctx, unit );

diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.h b/src/mesa/drivers/dri/radeon/radeon_common_context.h
index c9be104578ed47e98d0c7c6c6bf8abb226ded848..7618b3482f30ca80eac711ac2dcb044218ac1ccc 100644 (file)
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.h
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.h
@@ -170,7 +170,6 @@ typedef struct radeon_tex_obj radeonTexObj, *radeonTexObjPtr;
 /* Texture object in locally shared texture space.
  */
 struct radeon_tex_obj {
-  //   driTextureObject base;
        struct gl_texture_object base;
        struct _radeon_mipmap_tree *mt;
 
@@ -185,26 +184,9 @@ struct radeon_tex_obj {
        GLuint tile_bits;       /* hw texture tile bits used on this texture */
         struct radeon_bo *bo;
 
-       GLuint bufAddr;         /* Offset to start of locally
-                                  shared texture block */
-
-       GLuint dirty_state;     /* Flags (1 per texunit) for
-                                  whether or not this texobj
-                                  has dirty hardware state
-                                  (pp_*) that needs to be
-                                  brought into the
-                                  texunit. */
-
-       drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS];
-       /* Six, for the cube faces */
-
-
-
        GLuint pp_txfilter;     /* hardware register values */
        GLuint pp_txformat;
-        GLuint pp_txformat_x;
-       GLuint pp_txoffset;     /* Image location in texmem.
-                                  All cube faces follow. */
+       GLuint pp_txformat_x;
        GLuint pp_txsize;       /* npot only */
        GLuint pp_txpitch;      /* npot only */
        GLuint pp_border_color;

diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c
index 998ae796240aac9b444ee4fde87bcb77f70a7b37..617e731a4113d8489674aae496d41d28acd8ce1e 100644 (file)
--- a/src/mesa/drivers/dri/radeon/radeon_state_init.c
+++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c
@@ -486,7 +486,7 @@ static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom)
      OUT_BATCH(r100->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]);
      //     OUT_BATCH(r100->radeon.radeonScreen);
    } else if (t->image_override)
-     OUT_BATCH(atom->cmd[4]);
+     OUT_BATCH(t->override_offset);
 
    OUT_BATCH_TABLE((atom->cmd+4), 5);
    END_BATCH();

diff --git a/src/mesa/drivers/dri/radeon/radeon_tex.c b/src/mesa/drivers/dri/radeon/radeon_tex.c
index 4d98b72612b1a3f8c0a3d94a09d2d49263d7bc13..2dfb5042ecc23d5db5b69029b2f9c31290e3f725 100644 (file)
--- a/src/mesa/drivers/dri/radeon/radeon_tex.c
+++ b/src/mesa/drivers/dri/radeon/radeon_tex.c
@@ -362,10 +362,6 @@ static void radeonTexParameter( GLcontext *ctx, GLenum target,
    default:
       return;
    }
-
-   /* Mark this texobj as dirty (one bit per tex unit)
-    */
-   t->dirty_state = R100_TEX_ALL;
 }
 
 static void radeonDeleteTexture( GLcontext *ctx,

diff --git a/src/mesa/drivers/dri/radeon/radeon_texstate.c b/src/mesa/drivers/dri/radeon/radeon_texstate.c
index 2aa1a833420d7a9a1d39f686b023dab03fae9238..6a34f1e33283e166a47722848b847074e70af116 100644 (file)
--- a/src/mesa/drivers/dri/radeon/radeon_texstate.c
+++ b/src/mesa/drivers/dri/radeon/radeon_texstate.c
@@ -614,8 +614,9 @@ void radeonSetTexOffset(__DRIcontext * pDRICtx, GLint texname,
 
        if (!offset)
                return;
-
-       t->pp_txoffset = offset;
+       
+       t->bo = NULL;
+       t->override_offset = offset;
        t->pp_txpitch = pitch - 32;
 
        switch (depth) {
@@ -715,7 +716,6 @@ static void import_tex_obj_state( r100ContextPtr rmesa,
    cmd[TEX_PP_TXFILTER] |= texobj->pp_txfilter & TEXOBJ_TXFILTER_MASK;
    cmd[TEX_PP_TXFORMAT] &= ~TEXOBJ_TXFORMAT_MASK;
    cmd[TEX_PP_TXFORMAT] |= texobj->pp_txformat & TEXOBJ_TXFORMAT_MASK;
-   cmd[TEX_PP_TXOFFSET] = texobj->pp_txoffset;
    cmd[TEX_PP_BORDER_COLOR] = texobj->pp_border_color;
 
    if (texobj->base.Target == GL_TEXTURE_RECTANGLE_NV) {
@@ -742,8 +742,6 @@ static void import_tex_obj_state( r100ContextPtr rmesa,
       rmesa->hw.set.cmd[SET_SE_COORDFMT] = se_coord_fmt;
    }
 
-   texobj->dirty_state &= ~(1<<unit);
-
    rmesa->radeon.NewGLState |= _NEW_TEXTURE_MATRIX;
 }
 
@@ -974,7 +972,6 @@ static GLboolean setup_hardware_state(r100ContextPtr rmesa, radeonTexObj *t, int
       t->pp_txformat |= RADEON_TXFORMAT_NON_POWER2;
    }
 
-   t->dirty_state = R100_TEX_ALL;
    return GL_TRUE;
 }
 
@@ -1004,9 +1001,7 @@ static GLboolean radeon_validate_texture(GLcontext *ctx, struct gl_texture_objec
 
    rmesa->recheck_texgen[unit] = GL_TRUE;
 
-   if (t->dirty_state & (1<<unit)) {
-      import_tex_obj_state( rmesa, unit, t );
-   }
+   import_tex_obj_state( rmesa, unit, t );
 
    if (rmesa->recheck_texgen[unit]) {
       GLboolean fallback = !radeon_validate_texgen( ctx, unit );