fix typos

diff --git a/openpower/sv/rfc/ls003.mdwn b/openpower/sv/rfc/ls003.mdwn
index f5204c3203caf14a456ce035ebc9e47559bb0a87..da98601b06ece7e0223ec7f975dcb3b675c27e47 100644 (file)
--- a/openpower/sv/rfc/ls003.mdwn
+++ b/openpower/sv/rfc/ls003.mdwn
@@ -131,7 +131,7 @@ The low-order 64 bits of the 128-bit sum are
 placed into register RT.
 The high-order 64 bits of the 128-bit sum are
 placed into register RS.
-RS is implictly defined as the same register as RC.
+RS is implicitly defined as the same register as RC.
 
 All three operands and the result are interpreted as
 unsigned integers.
@@ -149,8 +149,8 @@ To achieve a big-integer rolling-accumulation effect:
 assuming the scalar to multiply is in r0, and r3 is
 used (effectively) as a 64-bit carry,
 the vector to multiply by starts at r4 and the result vector
-in r20, instructions may be issued `maddedu r20,r4,r0,r3
-maddedu r21,r5,r0,r3` etc. where the first `maddedu` will have
+in r20, instructions may be issued `maddedu r20,r4,r0,r3`
+`maddedu r21,r5,r0,r3` etc. where the first `maddedu` will have
 stored the upper half of the 128-bit multiply into r3, such
 that it may be picked up by the second `maddedu`. Repeat inline
 to construct a larger bigint scalar-vector multiply,
@@ -208,7 +208,7 @@ Special registers altered:
 The 128-bit dividend is (RA) || (RC). The 64-bit divisor is
 (RB). If the quotient can be represented in 64 bits, it is
 placed into register RT. The modulo is placed into register RS.
-RS is implictly defined as the same register as RC, similarly to maddedu.
+RS is implicitly defined as the same register as RC, similarly to maddedu.
 
 The quotient can be represented in 64-bits when both these conditions
 are true: