+2017-06-07 Michael Collison <michael.collison@arm.com>
+
+ * config/tc-aarch64.c (reg_entry_reg_names): Add IP0,
+ IP1, FP, and LR as register aliases of register 16, 17, 29
+ and 30 respectively.
+ * testsuite/gas/aarch64/diagnostic.l: Remove diagnostic
+ prohibiting register 'lr' which is now an alias.
+ * testsuite/gas/aarch64/diagnostic.s: Remove instruction
+ utilizing register 'lr' which is now an alias.
+
2017-06-06 Jiong Wang <jiong.wang@arm.com>
* config/tc-arm.c (reject_bad_reg): Allow REG_SP on ARMv8-A.
REGDEF (wzr, 31, Z_32), REGDEF (WZR, 31, Z_32),
REGDEF (xzr, 31, Z_64), REGDEF (XZR, 31, Z_64),
+ REGDEF (ip0, 16, R_64), REGDEF (IP0, 16, R_64),
+ REGDEF (ip1, 17, R_64), REGDEF (IP1, 17, R_64),
+ REGDEF (fp, 29, R_64), REGDEF (FP, 29, R_64),
+ REGDEF (lr, 30, R_64), REGDEF (LR, 30, R_64),
+
/* Floating-point single precision registers. */
REGSET (s, FP_S), REGSET (S, FP_S),
[^:]*:100: Error: operand 3 must be one of the standard conditions, excluding AL and NV. -- `cinc w0,w1,nv'
[^:]*:101: Error: operand 2 must be one of the standard conditions, excluding AL and NV. -- `cset w0,al'
[^:]*:102: Error: operand 2 must be one of the standard conditions, excluding AL and NV. -- `cset w0,nv'
-[^:]*:105: Error: operand 1 must be an integer register -- `ret lr'
[^:]*:106: Error: operand 1 must be an integer register -- `ret kk'
[^:]*:107: Error: immediate operand required at operand 1 -- `clrex x0'
[^:]*:108: Error: immediate operand required at operand 1 -- `clrex w0'