wf->decLGKMInstsIssued();
wf->rdGmReqsInPipe--;
wf->rdLmReqsInPipe--;
+ gpuDynInst->exec_mask = wf->execMask();
+ wf->computeUnit->vrf[wf->simdId]->
+ scheduleWriteOperandsFromLoad(wf, gpuDynInst);
return;
}
wf->decLGKMInstsIssued();
wf->rdGmReqsInPipe--;
wf->rdLmReqsInPipe--;
+ gpuDynInst->exec_mask = wf->execMask();
+ wf->computeUnit->vrf[wf->simdId]->
+ scheduleWriteOperandsFromLoad(wf, gpuDynInst);
return;
}
wf->decLGKMInstsIssued();
wf->rdGmReqsInPipe--;
wf->rdLmReqsInPipe--;
+ gpuDynInst->exec_mask = wf->execMask();
+ wf->computeUnit->vrf[wf->simdId]->
+ scheduleWriteOperandsFromLoad(wf, gpuDynInst);
return;
}
wf->decLGKMInstsIssued();
wf->rdGmReqsInPipe--;
wf->rdLmReqsInPipe--;
+ gpuDynInst->exec_mask = wf->execMask();
+ wf->computeUnit->vrf[wf->simdId]->
+ scheduleWriteOperandsFromLoad(wf, gpuDynInst);
return;
}
wf->decLGKMInstsIssued();
wf->rdGmReqsInPipe--;
wf->rdLmReqsInPipe--;
+ gpuDynInst->exec_mask = wf->execMask();
+ wf->computeUnit->vrf[wf->simdId]->
+ scheduleWriteOperandsFromLoad(wf, gpuDynInst);
return;
}
wf->decLGKMInstsIssued();
wf->rdGmReqsInPipe--;
wf->rdLmReqsInPipe--;
+ gpuDynInst->exec_mask = wf->execMask();
+ wf->computeUnit->vrf[wf->simdId]->
+ scheduleWriteOperandsFromLoad(wf, gpuDynInst);
+ return;
}
gpuDynInst->execUnitId = wf->execUnitId;
wf->decLGKMInstsIssued();
wf->wrGmReqsInPipe--;
wf->rdGmReqsInPipe--;
+ if (instData.GLC) {
+ gpuDynInst->exec_mask = wf->execMask();
+ wf->computeUnit->vrf[wf->simdId]->
+ scheduleWriteOperandsFromLoad(wf, gpuDynInst);
+ }
return;
}
wf->decLGKMInstsIssued();
wf->wrGmReqsInPipe--;
wf->rdGmReqsInPipe--;
+ if (instData.GLC) {
+ gpuDynInst->exec_mask = wf->execMask();
+ wf->computeUnit->vrf[wf->simdId]->
+ scheduleWriteOperandsFromLoad(wf, gpuDynInst);
+ }
return;
}
wf->decLGKMInstsIssued();
wf->wrGmReqsInPipe--;
wf->rdGmReqsInPipe--;
+ if (instData.GLC) {
+ gpuDynInst->exec_mask = wf->execMask();
+ wf->computeUnit->vrf[wf->simdId]->
+ scheduleWriteOperandsFromLoad(wf, gpuDynInst);
+ }
return;
}
wf->decLGKMInstsIssued();
wf->wrGmReqsInPipe--;
wf->rdGmReqsInPipe--;
+ if (instData.GLC) {
+ gpuDynInst->exec_mask = wf->execMask();
+ wf->computeUnit->vrf[wf->simdId]->
+ scheduleWriteOperandsFromLoad(wf, gpuDynInst);
+ }
return;
}
wf->decLGKMInstsIssued();
wf->wrGmReqsInPipe--;
wf->rdGmReqsInPipe--;
+ if (instData.GLC) {
+ gpuDynInst->exec_mask = wf->execMask();
+ wf->computeUnit->vrf[wf->simdId]->
+ scheduleWriteOperandsFromLoad(wf, gpuDynInst);
+ }
return;
}
wf->decLGKMInstsIssued();
wf->wrGmReqsInPipe--;
wf->rdGmReqsInPipe--;
+ if (instData.GLC) {
+ gpuDynInst->exec_mask = wf->execMask();
+ wf->computeUnit->vrf[wf->simdId]->
+ scheduleWriteOperandsFromLoad(wf, gpuDynInst);
+ }
return;
}
wf->decLGKMInstsIssued();
wf->wrGmReqsInPipe--;
wf->rdGmReqsInPipe--;
+ if (instData.GLC) {
+ gpuDynInst->exec_mask = wf->execMask();
+ wf->computeUnit->vrf[wf->simdId]->
+ scheduleWriteOperandsFromLoad(wf, gpuDynInst);
+ }
return;
}
wf->decLGKMInstsIssued();
wf->wrGmReqsInPipe--;
wf->rdGmReqsInPipe--;
+ if (instData.GLC) {
+ gpuDynInst->exec_mask = wf->execMask();
+ wf->computeUnit->vrf[wf->simdId]->
+ scheduleWriteOperandsFromLoad(wf, gpuDynInst);
+ }
return;
}
wf->decLGKMInstsIssued();
wf->wrGmReqsInPipe--;
wf->rdGmReqsInPipe--;
+ if (instData.GLC) {
+ gpuDynInst->exec_mask = wf->execMask();
+ wf->computeUnit->vrf[wf->simdId]->
+ scheduleWriteOperandsFromLoad(wf, gpuDynInst);
+ }
return;
}
wf->decLGKMInstsIssued();
wf->wrGmReqsInPipe--;
wf->rdGmReqsInPipe--;
+ if (instData.GLC) {
+ gpuDynInst->exec_mask = wf->execMask();
+ wf->computeUnit->vrf[wf->simdId]->
+ scheduleWriteOperandsFromLoad(wf, gpuDynInst);
+ }
return;
}
wf->decLGKMInstsIssued();
wf->wrGmReqsInPipe--;
wf->rdGmReqsInPipe--;
+ if (instData.GLC) {
+ gpuDynInst->exec_mask = wf->execMask();
+ wf->computeUnit->vrf[wf->simdId]->
+ scheduleWriteOperandsFromLoad(wf, gpuDynInst);
+ }
return;
}