use new submodules/specials/clock_domains automatic collection

diff --git a/lib/sata/phy/k7/crg.py b/lib/sata/phy/k7/crg.py
index 8b47b342c5f8b0ab79958081712bf6944f8ea1eb..3d008a67dcc1686b84cfd8e9c75afd476234500a 100644 (file)
--- a/lib/sata/phy/k7/crg.py
+++ b/lib/sata/phy/k7/crg.py
@@ -8,8 +8,8 @@ class K7SATAPHYCRG(Module):
                self.reset = Signal()
                self.ready = Signal()
 
-               self.clock_domains.cd_sata_tx = ClockDomain()
-               self.clock_domains.cd_sata_rx = ClockDomain()
+               self.cd_sata_tx = ClockDomain()
+               self.cd_sata_rx = ClockDomain()
 
        # CPLL
                # (SATA3) 150MHz / VCO @ 3GHz / Line rate @ 6Gbps

diff --git a/lib/sata/test/phy_datapath_tb.py b/lib/sata/test/phy_datapath_tb.py
index f195e561907b583230231d0099fb7c743fcd8e83..d91092f1f398e8efc3d5d85425511214bc657f28 100644 (file)
--- a/lib/sata/test/phy_datapath_tb.py
+++ b/lib/sata/test/phy_datapath_tb.py
@@ -45,8 +45,8 @@ class CTRL(Module):
 class TB(Module):
        def __init__(self):
                # use sys_clk for each clock_domain
-               self.clock_domains.cd_sata_rx = ClockDomain()
-               self.clock_domains.cd_sata_tx = ClockDomain()
+               self.cd_sata_rx = ClockDomain()
+               self.cd_sata_tx = ClockDomain()
                self.comb += [
                        self.cd_sata_rx.clk.eq(ClockSignal()),
                        self.cd_sata_rx.rst.eq(ResetSignal()),

diff --git a/targets/test.py b/targets/test.py
index ee38e0d0f43a837381359e2683c90e8ea0765cd2..850086ee3a4d626e7fddde736c28a98a26fafe4f 100644 (file)
--- a/targets/test.py
+++ b/targets/test.py
@@ -19,8 +19,8 @@ from migen.genlib.cdc import *
 
 class _CRG(Module):
        def __init__(self, platform):
-               self.clock_domains.cd_sys = ClockDomain()
-               self.clock_domains.cd_por = ClockDomain(reset_less=True)
+               self.cd_sys = ClockDomain()
+               self.cd_por = ClockDomain(reset_less=True)
 
                clk200 = platform.request("clk200")
                clk200_se = Signal()