ARM: Ignore/warn on iciallu.

diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index e51f0ddd6d844edb6e4175a1c8f3cd1e03f40e82..e4245af333ae09db2fdb2e8a6a90aa61f5031eb1 100644 (file)
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -94,6 +94,7 @@ namespace ArmISA
         MISCREG_CPACR,
         MISCREG_CLIDR,
         MISCREG_ICIALLUIS,
+        MISCREG_ICIALLU,
         MISCREG_CP15_UNIMP_START,
         MISCREG_CTR = MISCREG_CP15_UNIMP_START,
         MISCREG_TCMTR,
@@ -132,7 +133,6 @@ namespace ArmISA
         MISCREG_IRACR,
         MISCREG_RGNR,
         MISCREG_BPIALLIS,
-        MISCREG_ICIALLU,
         MISCREG_ICIMVAU,
         MISCREG_BPIALL,
         MISCREG_BPIMVA,
@@ -160,7 +160,8 @@ namespace ArmISA
         "fpsr", "fpsid", "fpscr", "fpexc",
         "sctlr", "dccisw", "dccimvac",
         "contextidr", "tpidrurw", "tpidruro", "tpidrprw",
-        "cp15isb", "cp15dsb", "cp15dmb", "cpacr", "clidr", "icialluis",
+        "cp15isb", "cp15dsb", "cp15dmb", "cpacr", "clidr",
+        "icialluis", "iciallu",
         "ctr", "tcmtr", "mpuir", "mpidr", "midr",
         "id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
         "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
@@ -168,7 +169,7 @@ namespace ArmISA
         "ccsidr", "aidr", "csselr", "actlr",
         "dfsr", "ifsr", "adfsr", "aifsr", "dfar", "ifar",
         "drbar", "irbar", "drsr", "irsr", "dracr", "iracr",
-        "rgnr", "bpiallis", "iciallu", "icimvau",
+        "rgnr", "bpiallis", "icimvau",
         "bpiall", "bpimva", "dcimvac", "dcisw", "dccmvac", "mccsw",
         "dccmvau",
         "nop", "raz"