I ran a script that shouldn't have missed any tab in the python source files.
Subsignal("tx", Pins("K26")),
Subsignal("rx", Pins("G25")),
IOStandard("LVCMOS18")
- ),
+ ),
("spiflash", 0, # clock needs to be accessed through primitive
Subsignal("cs_n", Pins("U7")),
drdy = Signal()
self.specials += Instance("XADC",
- # from ug480
+ # from ug480
p_INIT_40=0x9000, p_INIT_41=0x2ef0, p_INIT_42=0x0400,
p_INIT_48=0x4701, p_INIT_49=0x000f,
p_INIT_4A=0x4700, p_INIT_4B=0x0000,
if c == b"\r":
sys.stdout.buffer.write(b"\n")
else:
- sys.stdout.buffer.write(c)
+ sys.stdout.buffer.write(c)
sys.stdout.flush()
if self.kernel_image is not None:
if packet == 0:
break
except:
- break
+ break
packet = EtherbonePacket(packet)
packet.decode()