Fix wire width

diff --git a/tests/various/submod.ys b/tests/various/submod.ys
index f50556d769b73011c40d51cccc8c4f9c12571ccd..a0a3f2da58cab5885584ff69d9c7460b6b9b7681 100644 (file)
--- a/tests/various/submod.ys
+++ b/tests/various/submod.ys
@@ -1,8 +1,8 @@
 read_verilog <<EOT
-module top(input a, output [1:0] b);
+module top(input a, output b);
 wire c;
 (* submod="bar" *) sub s1(a, c);
-assign b[0] = c;
+assign b = c;
 endmodule
 
 module sub(input a, output c);