* sim/cris/asm/movmp8.ms, sim/cris/asm/pcplus.ms: New tests.

	* sim/cris/asm/movmp.ms: Do not write to P0, P4 or P8.
	* sim/cris/asm/raw13.ms: Write to MOF instead of WZ (P4).

diff --git a/sim/testsuite/ChangeLog b/sim/testsuite/ChangeLog
index 2b794d5477bd77dce94454a5b5e13b0ea391abbe..20c2c520ffdca17230796b78bf6e02925a3c817f 100644 (file)
--- a/sim/testsuite/ChangeLog
+++ b/sim/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2005-12-06  Hans-Peter Nilsson  <hp@axis.com>
+
+       * sim/cris/asm/movmp8.ms, sim/cris/asm/pcplus.ms: New tests.
+       * sim/cris/asm/movmp.ms: Do not write to P0, P4 or P8.
+       * sim/cris/asm/raw13.ms: Write to MOF instead of WZ (P4).
+
 2005-11-21  Hans-Peter Nilsson  <hp@axis.com>
 
        * sim/cris: New directory with C and assembly tests for the CRIS

diff --git a/sim/testsuite/sim/cris/asm/movmp.ms b/sim/testsuite/sim/cris/asm/movmp.ms
index 7080d71f713638475c4efc40aca4277d563aeb26..d864692cefc6a8718cb27002ec3daded15c599e3 100644 (file)
--- a/sim/testsuite/sim/cris/asm/movmp.ms
+++ b/sim/testsuite/sim/cris/asm/movmp.ms
@@ -16,9 +16,14 @@ filler:
 
  .text
 ; Test that writing to zero-registers is a nop
+ .if 0
+ ; We used to just ignore the writes, but now an error is emitted.  We
+ ; keep the test-code but disabled, in case we need to change this again.
  move 0xaa,p0
  move 0x4433,p4
  move 0x55774433,p8
+ .endif
+
  moveq -1,r3
  setf zcvn
  clear.b r3
@@ -36,10 +41,13 @@ filler:
  dumpr3
 
 ; "Write" using ordinary memory references too.
+ .if 0 ; See ".if 0" above.
  move.d filler,r6
  move [r6],p0
  move [r6],p4
  move [r6],p8
+ .endif
+
  moveq -1,r3
  clear.b r3
  dumpr3
@@ -53,9 +61,12 @@ filler:
  dumpr3
 
 ; And postincremented.
+ .if 0 ; See ".if 0" above.
  move [r6+],p0
  move [r6+],p4
  move [r6+],p8
+ .endif
+
  moveq -1,r3
  clear.b r3
  dumpr3

diff --git a/sim/testsuite/sim/cris/asm/movmp8.ms b/sim/testsuite/sim/cris/asm/movmp8.ms
new file mode 100644 (file)
index 0000000..ffb3854
--- /dev/null
+++ b/sim/testsuite/sim/cris/asm/movmp8.ms
@@ -0,0 +1,33 @@
+# mach: crisv3 crisv8 crisv10
+
+# Make sure that "move [$sp=$sp+16],$p8" works; used in Linux.
+
+ .include "testutils.inc"
+ startnostack
+ move.d x,$sp
+ moveq 0,$r3
+ move [$sp=$sp+16],$p8
+ ; Z not changed.
+ bne 0f
+ nop
+ cmp.d x+16,$sp
+ bne 0f
+ nop
+ move $p8,$r3
+ ; Z not changed.
+ bne 0f
+ ; P8 still 0.
+ test.d $r3
+ bne 0f
+ nop
+ pass
+0:
+ fail
+
+ .data
+x:
+ .dword 0xffffffff
+ .dword 0xffffffff
+ .dword 0xffffffff
+ .dword 0xffffffff
+ .dword 0xffffffff

diff --git a/sim/testsuite/sim/cris/asm/pcplus.ms b/sim/testsuite/sim/cris/asm/pcplus.ms
new file mode 100644 (file)
index 0000000..99cd46a
--- /dev/null
+++ b/sim/testsuite/sim/cris/asm/pcplus.ms
@@ -0,0 +1,46 @@
+# mach: crisv0 crisv3 crisv8 crisv10
+
+; Test that a forward as well as backward 32-bit "branch" expansion
+; works including that the right offset is applied.
+
+       .macro nop32
+       .rept 32
+       nop
+       .endr
+       .endm
+
+       .include "testutils.inc"
+       start
+       jump start1
+       fail
+
+       nop32
+       subq 63,$r10
+9:     subq 1,$r10
+       nop32
+       jump 0f
+
+       fail
+0:     move [$pc=$pc+1f-6-0b],$p0
+       nop32
+       fail
+
+       .skip 32768,0
+
+       nop32
+       subq 63,$r10
+1:
+       subq 1,$r10
+       nop32
+       test.d $r10
+       bne 7f
+       nop
+       pass
+7:
+       fail
+
+start1:
+       moveq 2,$r10
+0:     move [$pc=$pc+9b-6-0b],$p0
+       subq 63,$r10
+       fail

diff --git a/sim/testsuite/sim/cris/asm/raw13.ms b/sim/testsuite/sim/cris/asm/raw13.ms
index a4175c477df3ada9ae6040f2d87e1805c383c09b..e5e2e525dda1b8074bc2c1357683175b33f52807 100644 (file)
--- a/sim/testsuite/sim/cris/asm/raw13.ms
+++ b/sim/testsuite/sim/cris/asm/raw13.ms
@@ -1,4 +1,4 @@
-; Checking read-after-write: write-WZ-then-read unaffected.
+; Checking read-after-write: write-MOF-then-read unaffected.
 #mach: crisv32
 #output: Basic clock cycles, total @: 4\n
 #output: Memory source stall cycles: 0\n
@@ -17,6 +17,6 @@
  .lcomm y,4
  move.d x,$r0
  move.d y,$r1
- move [$r0],$wz
+ move [$r0],$mof
  move [$r1],$srp
  break 15