back.rtlil: update for Yosys master.

diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py
index 67371308d91ce65c5dfb2697006543740fe62cef..70b9596a4217925ea2dc4058ab3d49ffc2b7f2e9 100644 (file)
--- a/nmigen/back/rtlil.py
+++ b/nmigen/back/rtlil.py
@@ -451,9 +451,7 @@ class _RHSValueCompiler(_ValueCompiler):
             raise TypeError # :nocov:
 
     def _prepare_value_for_Slice(self, value):
-        # Uncomment after the following is merged: https://github.com/YosysHQ/yosys/pull/741
-        # if isinstance(value, (ast.Signal, ast.Slice, ast.Cat)):
-        if isinstance(value, ast.Signal):
+        if isinstance(value, (ast.Signal, ast.Slice, ast.Cat)):
             sigspec = self(value)
         else:
             sigspec = self.s.rtlil.wire(len(value))