2000-02-22 Andrew Haley <aph@cygnus.com>

        * doc/c-mips.texi (MIPS Opts): Document -mgp32 and -mgp64.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 2653bef70389fc22b38c642ce9c6e5051e814aa6..218e2180ecb1176dea0ec5609ac8c494487f8731 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,7 @@
+2000-02-22  Andrew Haley  <aph@cygnus.com>
+
+       * doc/c-mips.texi (MIPS Opts): Document -mgp32 and -mgp64.
+
 1999-12-30  Andrew Haley  <aph@cygnus.com>
 
        * config/tc-mips.c (mips_gp32): New variable.

diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi
index fc2555a172ae205c72fdc204eaef75dd45f8c99e..6234b0c0b7d9b33a14649e28013a973abdae480c 100644 (file)
--- a/gas/doc/c-mips.texi
+++ b/gas/doc/c-mips.texi
@@ -67,6 +67,19 @@ Generate code for a particular MIPS Instruction Set Architecture level.
 @sc{r10000} processors.  You can also switch instruction sets during the
 assembly; see @ref{MIPS ISA,, Directives to override the ISA level}.
 
+@item -mgp32
+Assume that 32-bit general purpose registers are available.  This
+affects synthetic instructions such as @code{move}, which will assemble
+to a 32-bit or a 64-bit instruction depending on this flag.  On some
+MIPS variants there is be a 32-bit mode flag; when this flag is set,
+64-bit instructions generate a trap.  Also, some 32-bit OSes only save
+the 32-bit registers on a context switch, so it is essential never to
+use the 64-bit registers.
+
+@item -mgp64
+Assume that 64-bit general purpose registers are available.  This is
+provided in the interests of symmetry with -gp32.
+
 @item -mips16
 @itemx -no-mips16
 Generate code for the MIPS 16 processor.  This is equivalent to putting