L1IcacheMemory = l1i_cache,
L1DcacheMemory = l1d_cache,
l2_select_num_bits = l2_bits,
+ send_evictions = (
+ options.cpu_type == "detailed"),
ruby_system = ruby_system)
cpu_seq = RubySequencer(version = i,
l1_cntrl = L1Cache_Controller(version = i,
cntrl_id = cntrl_count,
cacheMemory = cache,
+ send_evictions = (
+ options.cpu_type == "detailed"),
ruby_system = ruby_system)
cpu_seq = RubySequencer(version = i,
L1IcacheMemory = l1i_cache,
L1DcacheMemory = l1d_cache,
l2_select_num_bits = l2_bits,
+ send_evictions = (
+ options.cpu_type == "detailed"),
ruby_system = ruby_system)
cpu_seq = RubySequencer(version = i,
not options.disable_dyn_timeouts,
no_mig_atomic = not \
options.allow_atomic_migration,
+ send_evictions = (
+ options.cpu_type == "detailed"),
ruby_system = ruby_system)
cpu_seq = RubySequencer(version = i,
L2cacheMemory = l2_cache,
no_mig_atomic = not \
options.allow_atomic_migration,
+ send_evictions = (
+ options.cpu_type == "detailed"),
ruby_system = ruby_system)
cpu_seq = RubySequencer(version = i,
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-machine(L1Cache, "MSI Directory L1 Cache CMP")
+machine(L1Cache, "MESI Directory L1 Cache CMP")
: Sequencer * sequencer,
CacheMemory * L1IcacheMemory,
CacheMemory * L1DcacheMemory,
int l2_select_num_bits,
int l1_request_latency = 2,
int l1_response_latency = 2,
- int to_l2_latency = 1
+ int to_l2_latency = 1,
+ bool send_evictions
{
// NODE L1 CACHE
// From this node's L1 cache TO the network
IS_I, AccessPermission:Busy, desc="L1 idle, issued GETS, saw Inv before data because directory doesn't block on GETS hit";
M_I, AccessPermission:Busy, desc="L1 replacing, waiting for ACK";
- E_I, AccessPermission:Busy, desc="L1 replacing, waiting for ACK";
SINK_WB_ACK, AccessPermission:Busy, desc="This is to sink WB_Acks from L2";
}
}
}
+ action(forward_eviction_to_cpu, "\cc", desc="sends eviction information to the processor") {
+ if (send_evictions) {
+ DPRINTF(RubySlicc, "Sending invalidation for %s to the CPU\n", address);
+ sequencer.evictionCallback(address);
+ }
+ }
action(g_issuePUTX, "g", desc="send data to the L2 cache") {
enqueue(requestIntraChipL1Network_out, RequestMsg, latency=l1_response_latency) {
//*****************************************************
// Transitions for Load/Store/Replacement/WriteBack from transient states
- transition({IS, IM, IS_I, M_I, E_I, SM}, {Load, Ifetch, Store, L1_Replacement}) {
+ transition({IS, IM, IS_I, M_I, SM}, {Load, Ifetch, Store, L1_Replacement}) {
z_recycleMandatoryQueue;
}
}
transition(S, L1_Replacement, I) {
+ forward_eviction_to_cpu;
ff_deallocateL1CacheBlock;
}
transition(S, Inv, I) {
+ forward_eviction_to_cpu;
fi_sendInvAck;
l_popRequestQueue;
}
transition(E, L1_Replacement, M_I) {
// silent E replacement??
+ forward_eviction_to_cpu;
i_allocateTBE;
g_issuePUTX; // send data, but hold in case forwarded request
ff_deallocateL1CacheBlock;
transition(E, Inv, I) {
// don't send data
+ forward_eviction_to_cpu;
fi_sendInvAck;
l_popRequestQueue;
}
transition(E, Fwd_GETX, I) {
+ forward_eviction_to_cpu;
d_sendDataToRequestor;
l_popRequestQueue;
}
}
transition(M, L1_Replacement, M_I) {
+ forward_eviction_to_cpu;
i_allocateTBE;
g_issuePUTX; // send data, but hold in case forwarded request
ff_deallocateL1CacheBlock;
}
transition(M, Inv, I) {
+ forward_eviction_to_cpu;
f_sendDataToL2;
l_popRequestQueue;
}
}
transition(M, Fwd_GETX, I) {
+ forward_eviction_to_cpu;
d_sendDataToRequestor;
l_popRequestQueue;
}
o_popIncomingResponseQueue;
}
-
transition(IS, DataS_fromL1, S) {
u_writeDataToL1Cache;
j_sendUnblock;
transition(SINK_WB_ACK, {Load, Store, Ifetch, L1_Replacement}){
z_recycleMandatoryQueue;
-
}
transition(SINK_WB_ACK, Inv){
o_popIncomingResponseQueue;
}
}
-
-
-
: Sequencer * sequencer,
CacheMemory * cacheMemory,
int cache_response_latency = 12,
- int issue_latency = 2
+ int issue_latency = 2,
+ bool send_evictions
{
// NETWORK BUFFERS
DataBlock DataBlk, desc="Data in the block";
}
-
// TBE fields
structure(TBE, desc="...") {
State TBEState, desc="Transient state";
// STRUCTURES
-
TBETable TBEs, template_hack="<L1Cache_TBE>";
// PROTOTYPES
}
}
-
action(e_sendData, "e", desc="Send data from cache to requestor") {
peek(forwardRequestNetwork_in, RequestMsg) {
enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) {
}
}
+ action(forward_eviction_to_cpu, "\cc", desc="sends eviction information to the processor") {
+ if (send_evictions) {
+ DPRINTF(RubySlicc, "Sending invalidation for %s to the CPU\n", address);
+ sequencer.evictionCallback(address);
+ }
+ }
action(v_allocateTBE, "v", desc="Allocate TBE") {
TBEs.allocate(address);
set_tbe(TBEs[address]);
}
-
action(w_deallocateTBE, "w", desc="Deallocate TBE") {
TBEs.deallocate(address);
unset_tbe();
transition(M, Fwd_GETX, I) {
e_sendData;
+ forward_eviction_to_cpu;
o_popForwardedRequestQueue;
}
v_allocateTBE;
b_issuePUT;
x_copyDataFromCacheToTBE;
+ forward_eviction_to_cpu;
h_deallocateL1CacheBlock;
}
o_popForwardedRequestQueue;
}
}
-
CacheMemory * L1IcacheMemory,
CacheMemory * L1DcacheMemory,
int l2_select_num_bits,
- int request_latency = 2
+ int request_latency = 2,
+ bool send_evictions
{
// NODE L1 CACHE
}
}
-
action(ee_sendDataExclusive, "\e", desc="Send data from cache to requestor, don't keep a shared copy") {
peek(requestNetwork_in, RequestMsg) {
assert(is_valid(cache_entry));
useTimerTable.set(address, 50);
}
-
action(ub_dmaUnblockL2Cache, "ub", desc="Send dma ack to l2 cache") {
peek(requestNetwork_in, RequestMsg) {
enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
}
}
-
// L2 will usually request data for a writeback
action(qq_sendWBDataFromTBEToL2, "\q", desc="Send data from TBE to L2") {
enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
//assert(in_msg.Dirty == false);
}
}
-
}
action(v_writeDataToCacheVerify, "v", desc="Write data to cache, assert it was same as before") {
}
}
-
+ action(forward_eviction_to_cpu, "\cc", desc="sends eviction information to the processor") {
+ if (send_evictions) {
+ DPRINTF(RubySlicc, "Sending invalidation for %s to the CPU\n", address);
+ sequencer.evictionCallback(address);
+ }
+ }
action(uu_profileMiss, "\u", desc="Profile the demand miss") {
peek(mandatoryQueue_in, RubyRequest) {
transition(S, L1_Replacement, SI) {
i_allocateTBE;
dd_issuePUTS;
+ forward_eviction_to_cpu;
kk_deallocateL1CacheBlock;
}
transition(S, Inv, I) {
f_sendAck;
+ forward_eviction_to_cpu;
l_popForwardQueue;
}
transition(O, L1_Replacement, OI) {
i_allocateTBE;
dd_issuePUTO;
+ forward_eviction_to_cpu;
kk_deallocateL1CacheBlock;
}
transition(O, Fwd_GETX, I) {
ee_sendDataExclusive;
+ forward_eviction_to_cpu;
l_popForwardQueue;
}
transition(MM, L1_Replacement, MI) {
i_allocateTBE;
d_issuePUTX;
+ forward_eviction_to_cpu;
kk_deallocateL1CacheBlock;
}
transition(MM, Fwd_GETX, I) {
ee_sendDataExclusive;
+ forward_eviction_to_cpu;
l_popForwardQueue;
}
transition(MM, Fwd_GETS, I) {
ee_sendDataExclusive;
+ forward_eviction_to_cpu;
l_popForwardQueue;
}
transition(M, L1_Replacement, MI) {
i_allocateTBE;
d_issuePUTX;
+ forward_eviction_to_cpu;
kk_deallocateL1CacheBlock;
}
transition(M, Fwd_GETX, I) {
// e_sendData;
ee_sendDataExclusive;
+ forward_eviction_to_cpu;
l_popForwardQueue;
}
// Transitions from SM
transition(SM, Inv, IM) {
f_sendAck;
+ forward_eviction_to_cpu;
l_popForwardQueue;
}
int retry_threshold = 1,
int fixed_timeout_latency = 100,
bool dynamic_timeout_enabled = true,
- bool no_mig_atomic = true
+ bool no_mig_atomic = true,
+ bool send_evictions
{
// From this node's L1 cache TO the network
}
}
-
action(q_updateTokensFromResponse, "q", desc="Update the token count based on the incoming response message") {
peek(responseNetwork_in, ResponseMsg) {
assert(is_valid(cache_entry));
}
}
+ action(forward_eviction_to_cpu, "\cc", desc="sends eviction information to the processor") {
+ if (send_evictions) {
+ DPRINTF(RubySlicc, "Sending invalidation for %s to the CPU\n", address);
+ sequencer.evictionCallback(address);
+ }
+ }
+
action(uu_profileMiss, "\u", desc="Profile the demand miss") {
peek(mandatoryQueue_in, RubyRequest) {
if (L1DcacheMemory.isTagPresent(address)) {
zz_stallAndWaitMandatoryQueue;
}
-
// Lockdowns
transition({NP, I, S, O, M, MM, M_W, MM_W, IM, SM, OM, IS}, Own_Lock_or_Unlock) {
l_popPersistentQueue;
transition(S, L1_Replacement, I) {
ta_traceStalledAddress;
cc_sharedReplacement; // Only needed in some cases
+ forward_eviction_to_cpu;
gg_deallocateL1CacheBlock;
ka_wakeUpAllDependents;
}
transition(S, {Transient_GETX, Transient_Local_GETX}, I) {
t_sendAckWithCollectedTokens;
p_informL2AboutTokenLoss;
+ forward_eviction_to_cpu
m_popRequestQueue;
}
transition({S, S_L}, Persistent_GETX, I_L) {
e_sendAckWithCollectedTokens;
p_informL2AboutTokenLoss;
+ forward_eviction_to_cpu
l_popPersistentQueue;
}
transition(O, L1_Replacement, I) {
ta_traceStalledAddress;
c_ownedReplacement;
+ forward_eviction_to_cpu
gg_deallocateL1CacheBlock;
ka_wakeUpAllDependents;
}
transition(O, {Transient_GETX, Transient_Local_GETX}, I) {
dd_sendDataWithAllTokens;
p_informL2AboutTokenLoss;
+ forward_eviction_to_cpu
m_popRequestQueue;
}
transition(O, Persistent_GETX, I_L) {
ee_sendDataWithAllTokens;
p_informL2AboutTokenLoss;
+ forward_eviction_to_cpu
l_popPersistentQueue;
}
transition(O, Persistent_GETS_Last_Token, I_L) {
fo_sendDataWithOwnerToken;
+ forward_eviction_to_cpu
l_popPersistentQueue;
}
transition(MM, L1_Replacement, I) {
ta_traceStalledAddress;
c_ownedReplacement;
+ forward_eviction_to_cpu
gg_deallocateL1CacheBlock;
ka_wakeUpAllDependents;
}
transition(MM, {Transient_GETX, Transient_Local_GETX, Transient_GETS, Transient_Local_GETS}, I) {
dd_sendDataWithAllTokens;
p_informL2AboutTokenLoss;
+ forward_eviction_to_cpu
m_popRequestQueue;
}
transition(MM, {Persistent_GETX, Persistent_GETS}, I_L) {
ee_sendDataWithAllTokens;
p_informL2AboutTokenLoss;
+ forward_eviction_to_cpu
l_popPersistentQueue;
}
transition(M, L1_Replacement, I) {
ta_traceStalledAddress;
c_ownedReplacement;
+ forward_eviction_to_cpu
gg_deallocateL1CacheBlock;
ka_wakeUpAllDependents;
}
transition(M, {Transient_GETX, Transient_Local_GETX}, I) {
dd_sendDataWithAllTokens;
p_informL2AboutTokenLoss;
+ forward_eviction_to_cpu
m_popRequestQueue;
}
transition(M, Persistent_GETX, I_L) {
ee_sendDataWithAllTokens;
p_informL2AboutTokenLoss;
+ forward_eviction_to_cpu
l_popPersistentQueue;
}
transition(M_W, Use_TimeoutStarverX, I_L) {
s_deallocateTBE;
ee_sendDataWithAllTokens;
+ forward_eviction_to_cpu;
p_informL2AboutTokenLoss;
jj_unsetUseTimer;
}
-
-
// migratory
transition(MM_W, {Use_TimeoutStarverX, Use_TimeoutStarverS}, I_L) {
s_deallocateTBE;
ee_sendDataWithAllTokens;
+ forward_eviction_to_cpu;
p_informL2AboutTokenLoss;
jj_unsetUseTimer;
}
-
// Transient_GETX and Transient_GETS in transient states
transition(OM, {Transient_GETX, Transient_Local_GETX, Transient_GETS, Transient_GETS_Last_Token, Transient_Local_GETS_Last_Token, Transient_Local_GETS}) {
m_popRequestQueue; // Even if we have the data, we can pretend we don't have it yet.
transition({SM, SM_L}, Persistent_GETX, IM_L) {
e_sendAckWithCollectedTokens;
+ forward_eviction_to_cpu
l_popPersistentQueue;
}
transition(OM, Persistent_GETX, IM_L) {
ee_sendDataWithAllTokens;
+ forward_eviction_to_cpu
l_popPersistentQueue;
}
transition({IM, SM}, {Transient_GETX, Transient_Local_GETX}, IM) { // We don't have the data yet, but we might have collected some tokens. We give them up here to avoid livelock
t_sendAckWithCollectedTokens;
+ forward_eviction_to_cpu;
m_popRequestQueue;
}
kd_wakeUpDependents;
}
-
// Own_Lock_or_Unlock
transition(I_L, Own_Lock_or_Unlock, I) {
kd_wakeUpDependents;
}
}
-
int cache_response_latency = 10,
int issue_latency = 2,
int l2_cache_hit_latency = 10,
- bool no_mig_atomic = true
+ bool no_mig_atomic = true,
+ bool send_evictions
{
// NETWORK BUFFERS
unset_cache_entry();
}
+ action(forward_eviction_to_cpu, "\cc", desc="sends eviction information to the processor") {
+ if (send_evictions) {
+ DPRINTF(RubySlicc, "Sending invalidation for %s to the CPU\n", address);
+ sequencer.evictionCallback(address);
+ }
+ }
+
action(uu_profileMiss, "\u", desc="Profile the demand miss") {
peek(mandatoryQueue_in, RubyRequest) {
if (L1IcacheMemory.isTagPresent(address)) {
i_allocateTBE;
bf_issueGETF;
uu_profileMiss;
+ forward_eviction_to_cpu;
gg_deallocateL1CacheBlock;
k_popMandatoryQueue;
}
transition(S, L2_Replacement, I) {
+ forward_eviction_to_cpu;
rr_deallocateL2CacheBlock;
ka_wakeUpAllDependents;
}
transition(S, {Other_GETX, Invalidate}, I) {
f_sendAck;
+ forward_eviction_to_cpu;
l_popForwardQueue;
}
bf_issueGETF;
p_decrementNumberOfMessagesByOne;
uu_profileMiss;
+ forward_eviction_to_cpu;
gg_deallocateL1CacheBlock;
k_popMandatoryQueue;
}
transition(O, L2_Replacement, OI) {
i_allocateTBE;
d_issuePUT;
+ forward_eviction_to_cpu;
rr_deallocateL2CacheBlock;
ka_wakeUpAllDependents;
}
transition(O, {Other_GETX, Invalidate}, I) {
e_sendData;
+ forward_eviction_to_cpu;
l_popForwardQueue;
}
i_allocateTBE;
bf_issueGETF;
p_decrementNumberOfMessagesByOne;
+ forward_eviction_to_cpu;
gg_deallocateL1CacheBlock;
k_popMandatoryQueue;
}
transition(MM, L2_Replacement, MI) {
i_allocateTBE;
d_issuePUT;
+ forward_eviction_to_cpu;
rr_deallocateL2CacheBlock;
ka_wakeUpAllDependents;
}
transition(MM, {Other_GETX, Invalidate}, I) {
c_sendExclusiveData;
+ forward_eviction_to_cpu;
l_popForwardQueue;
}
transition(MM, Other_GETS, I) {
c_sendExclusiveData;
+ forward_eviction_to_cpu;
l_popForwardQueue;
}
transition(M, L2_Replacement, MI) {
i_allocateTBE;
d_issuePUT;
+ forward_eviction_to_cpu;
rr_deallocateL2CacheBlock;
ka_wakeUpAllDependents;
}
transition(M, {Other_GETX, Invalidate}, I) {
c_sendExclusiveData;
+ forward_eviction_to_cpu;
l_popForwardQueue;
}
transition(SM, {Other_GETX, Invalidate}, IM) {
f_sendAck;
+ forward_eviction_to_cpu;
l_popForwardQueue;
}
transition(SM_F, {Other_GETX, Invalidate}, IM_F) {
f_sendAck;
+ forward_eviction_to_cpu;
l_popForwardQueue;
}
transition(OM, {Other_GETX, Invalidate}, IM) {
e_sendData;
pp_incrementNumberOfMessagesByOne;
+ forward_eviction_to_cpu;
l_popForwardQueue;
}
transition(OM_F, {Other_GETX, Invalidate}, IM_F) {
q_sendDataFromTBEToCache;
pp_incrementNumberOfMessagesByOne;
+ forward_eviction_to_cpu;
l_popForwardQueue;
}
void writeCallback(Address, GenericMachineType, DataBlock, Time, Time, Time);
void checkCoherence(Address);
void profileNack(Address, int, int, uint64);
+ void evictionCallback(Address);
}
structure(RubyRequest, desc="...", interface="Message", external="yes") {
/*
* Copyright (c) 2009 Advanced Micro Devices, Inc.
+ * Copyright (c) 2011 Mark D. Hill and David A. Wood
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
{
return (unsigned) RubySystem::getBlockSizeBytes();
}
+
+void
+RubyPort::ruby_eviction_callback(const Address& address)
+{
+ DPRINTF(RubyPort, "Sending invalidations.\n");
+ Request req(address.getAddress(), 0, 0);
+ for (CpuPortIter it = cpu_ports.begin(); it != cpu_ports.end(); it++) {
+ Packet *pkt = new Packet(&req, MemCmd::InvalidationReq, -1);
+ (*it)->sendTiming(pkt);
+ }
+}
/*
* Copyright (c) 2009 Advanced Micro Devices, Inc.
+ * Copyright (c) 2011 Mark D. Hill and David A. Wood
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
RubySystem*_system, bool _access_phys_mem);
bool sendTiming(PacketPtr pkt);
void hitCallback(PacketPtr pkt);
+ void evictionCallback(const Address& address);
unsigned deviceBlockSize() const;
bool onRetryList()
protected:
const std::string m_name;
void ruby_hit_callback(PacketPtr pkt);
- void hit(PacketPtr pkt);
void testDrainComplete();
+ void ruby_eviction_callback(const Address& address);
int m_version;
AbstractController* m_controller;
g_system_ptr->checkGlobalCoherenceInvariant(addr);
#endif
}
+
+void
+Sequencer::evictionCallback(const Address& address)
+{
+ ruby_eviction_callback(address);
+}
void markRemoved();
void removeRequest(SequencerRequest* request);
+ void evictionCallback(const Address& address);
private:
void issueRequest(PacketPtr pkt, RubyRequestType type);
}
#endif // __MEM_RUBY_SYSTEM_SEQUENCER_HH__
-
projects / gem5.git / commitdiff