[AArch64 array_mode 8/8] Add d-registers to TARGET_ARRAY_MODE_SUPPORTED_P

gcc/:

	* config/aarch64/aarch64.h (AARCH64_VALID_SIMD_DREG_MODE): New.

	* config/aarch64/aarch64.c (aarch64_array_mode_supported_p): Add
	AARCH64_VALID_SIMD_DREG_MODE.

gcc/testsuite/:

	* gcc.target/aarch64/vect_int32x2x4_1.c: New.

From-SVN: r227794

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index a4911a0ff6a48baa8f25edd017b904cc6d11c07e..38719b9e03aad40fb42ad7328a90c225b900011b 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2015-09-15  Alan Lawrence  <alan.lawrence@arm.com>
+
+       * config/aarch64/aarch64.h (AARCH64_VALID_SIMD_DREG_MODE): New.
+
+       * config/aarch64/aarch64.c (aarch64_array_mode_supported_p): Add
+       AARCH64_VALID_SIMD_DREG_MODE.
+
 2015-09-15  Alan Lawrence  <alan.lawrence@arm.com>
 
        * config/aarch64/aarch64-simd.md (aarch64_ld2r<mode>,

diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 9c5cf4cb2752fd2d47127206df36a568d31350ea..bbac271488fc878b0e896a4b87dba0e86fccf680 100644 (file)
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -677,7 +677,8 @@ aarch64_array_mode_supported_p (machine_mode mode,
                                unsigned HOST_WIDE_INT nelems)
 {
   if (TARGET_SIMD
-      && AARCH64_VALID_SIMD_QREG_MODE (mode)
+      && (AARCH64_VALID_SIMD_QREG_MODE (mode)
+         || AARCH64_VALID_SIMD_DREG_MODE (mode))
       && (nelems >= 2 && nelems <= 4))
     return true;
 

diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index 9669e0148824b94c22695b9c1adc9164ce11192f..5a8db763222ac059d5ae4dc09d033d9bbfe56072 100644 (file)
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -872,6 +872,12 @@ extern enum aarch64_code_model aarch64_cmodel;
   (aarch64_cmodel == AARCH64_CMODEL_TINY               \
    || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC)
 
+/* Modes valid for AdvSIMD D registers, i.e. that fit in half a Q register.  */
+#define AARCH64_VALID_SIMD_DREG_MODE(MODE) \
+  ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \
+   || (MODE) == V2SFmode || (MODE) == V4HFmode || (MODE) == DImode \
+   || (MODE) == DFmode)
+
 /* Modes valid for AdvSIMD Q registers.  */
 #define AARCH64_VALID_SIMD_QREG_MODE(MODE) \
   ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 23558560441b1bda99629f7def6bdf2a2436d34a..6cea108480075c711c3057fb6a36cef4d1d884e5 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2015-09-15  Alan Lawrence  <alan.lawrence@arm.com>
+
+       * gcc.target/aarch64/vect_int32x2x4_1.c: New.
+
 2015-09-15  Richard Biener  <rguenther@suse.de>
 
        PR middle-end/67563

diff --git a/gcc/testsuite/gcc.target/aarch64/vect_int32x2x4_1.c b/gcc/testsuite/gcc.target/aarch64/vect_int32x2x4_1.c
new file mode 100644 (file)
index 0000000..734cfd6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/vect_int32x2x4_1.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -fdump-rtl-expand" } */
+
+#include <arm_neon.h>
+
+uint32x2x4_t
+test_1 (uint32x2x4_t a, uint32x2x4_t b)
+{
+   uint32x2x4_t result;
+
+   for (unsigned index = 0; index < 4; ++index)
+     result.val[index] = a.val[index] + b.val[index];
+
+   return result;
+}
+
+/* Should not use the stack in expand.  */
+/* { dg-final { scan-rtl-dump-not "virtual-stack-vars" "expand" } } */
+/* Should not have to modify the stack pointer.  */
+/* { dg-final { scan-assembler-not "\t(add|sub).*sp" } } */
+/* Should not have to store or load anything.  */
+/* { dg-final { scan-assembler-not "\t(ld|st)\[rp\]" } } */