arch-riscv: added support for pseudo instructions.

Change-Id: I4f73f8fcf62def8815e82555fc2a67f89efc09d1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25645
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

diff --git a/src/arch/riscv/insts/pseudo.hh b/src/arch/riscv/insts/pseudo.hh
new file mode 100644 (file)
index 0000000..47b11ad
--- /dev/null
+++ b/src/arch/riscv/insts/pseudo.hh
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2020 Barkhausen Institut
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ARCH_RISCV_INSTS_PSEUDO_HH__
+#define __ARCH_RISCV_INSTS_PSEUDO_HH__
+
+#include <string>
+
+#include "arch/riscv/insts/static_inst.hh"
+
+namespace RiscvISA
+{
+
+class PseudoOp : public RiscvStaticInst
+{
+  protected:
+    using RiscvStaticInst::RiscvStaticInst;
+
+    std::string generateDisassembly(
+        Addr pc, const SymbolTable *symtab) const override
+    {
+        return mnemonic;
+    }
+};
+
+}
+
+#endif // __ARCH_RISCV_INSTS_PSEUDO_HH__
\ No newline at end of file

diff --git a/src/arch/riscv/isa/bitfields.isa b/src/arch/riscv/isa/bitfields.isa
index dae7fe1a3934078e4dbf74076ef5f3202fe190c0..e32c82de53df6d39f6cdb460730837456cb9163b 100644 (file)
--- a/src/arch/riscv/isa/bitfields.isa
+++ b/src/arch/riscv/isa/bitfields.isa
@@ -2,6 +2,7 @@
 
 // Copyright (c) 2015 RISC-V Foundation
 // Copyright (c) 2016 The University of Virginia
+// Copyright (c) 2020 Barkhausen Institut
 // All rights reserved.
 //
 // Redistribution and use in source and binary forms, with or without
@@ -119,3 +120,6 @@ def bitfield CIMM5 <6:2>;
 def bitfield CIMM3 <12:10>;
 def bitfield CIMM2 <6:5>;
 def bitfield CIMM1 <12>;
+
+// Pseudo instructions
+def bitfield M5FUNC <31:25>;

diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index 63cf1e45ab6407857f6a289f0bd38d18286ab949..4f8fea2f9ce6ea0ff5b3a9c8bc7f0d2b26ab6ce2 100644 (file)
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -2,6 +2,7 @@
 
 // Copyright (c) 2015 RISC-V Foundation
 // Copyright (c) 2017 The University of Virginia
+// Copyright (c) 2020 Barkhausen Institut
 // All rights reserved.
 //
 // Redistribution and use in source and binary forms, with or without
@@ -1832,5 +1833,7 @@ decode QUADRANT default Unknown::unknown() {
                 }}, IsNonSpeculative, No_OpClass);
             }
         }
+
+        0x1e: M5Op::M5Op();
     }
 }

diff --git a/src/arch/riscv/isa/formats/formats.isa b/src/arch/riscv/isa/formats/formats.isa
index 0f7dc4274951c457997200716ece340563b0b9ca..2a6b91024d30de7674ea10f5c1f996de4f9f44ff 100644 (file)
--- a/src/arch/riscv/isa/formats/formats.isa
+++ b/src/arch/riscv/isa/formats/formats.isa
@@ -2,6 +2,7 @@
 
 // Copyright (c) 2015 RISC-V Foundation
 // Copyright (c) 2016-2017 The University of Virginia
+// Copyright (c) 2020 Barkhausen Institut
 // All rights reserved.
 //
 // Redistribution and use in source and binary forms, with or without
@@ -39,5 +40,8 @@
 // Include formats for nonstandard extensions
 ##include "compressed.isa"
 
+// Pseudo operations
+##include "m5ops.isa"
+
 // Include the unknown
 ##include "unknown.isa"

diff --git a/src/arch/riscv/isa/formats/m5ops.isa b/src/arch/riscv/isa/formats/m5ops.isa
new file mode 100644 (file)
index 0000000..2a16959
--- /dev/null
+++ b/src/arch/riscv/isa/formats/m5ops.isa
@@ -0,0 +1,47 @@
+//
+// Copyright (c) 2020 Barkhausen Institut
+// All rights reserved
+//
+// The license below extends only to copyright in the software and shall
+// not be construed as granting a license to any other intellectual
+// property including but not limited to intellectual property relating
+// to a hardware implementation of the functionality of the software
+// licensed hereunder.  You may use the software subject to the license
+// terms below provided that you ensure that this notice is replicated
+// unmodified and in its entirety in all distributions of the software,
+// modified or unmodified, in source code or in binary form.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+
+def format M5Op() {{
+    iop = InstObjParams(name, Name, 'PseudoOp',
+                        'a0 = PseudoInst::pseudoInst<PseudoInstABI>('
+                            + 'xc->tcBase(), M5FUNC)',
+                        ['IsNonSpeculative', 'IsSerializeAfter'])
+    header_output = BasicDeclare.subst(iop)
+    decoder_output = BasicConstructor.subst(iop)
+    decode_block = BasicDecode.subst(iop)
+    exec_output = BasicExecute.subst(iop)
+}};

diff --git a/src/arch/riscv/isa/includes.isa b/src/arch/riscv/isa/includes.isa
index 2d355bac0db49a60c5a1756c84fd5e0b73e67bdb..16114c95b6c33ec0d1c4e834b62dd29ff81cfef8 100644 (file)
--- a/src/arch/riscv/isa/includes.isa
+++ b/src/arch/riscv/isa/includes.isa
@@ -2,6 +2,7 @@
 
 // Copyright (c) 2015 RISC-V Foundation
 // Copyright (c) 2016 The University of Virginia
+// Copyright (c) 2020 Barkhausen Institut
 // All rights reserved.
 //
 // Redistribution and use in source and binary forms, with or without
@@ -42,6 +43,7 @@ output header {{
 #include "arch/riscv/insts/amo.hh"
 #include "arch/riscv/insts/compressed.hh"
 #include "arch/riscv/insts/mem.hh"
+#include "arch/riscv/insts/pseudo.hh"
 #include "arch/riscv/insts/standard.hh"
 #include "arch/riscv/insts/static_inst.hh"
 #include "arch/riscv/insts/unknown.hh"
@@ -90,6 +92,7 @@ output exec {{
 #include "mem/request.hh"
 #include "sim/eventq.hh"
 #include "sim/full_system.hh"
+#include "sim/pseudo_inst.hh"
 #include "sim/sim_events.hh"
 #include "sim/sim_exit.hh"
 #include "sim/system.hh"

diff --git a/src/arch/riscv/isa/operands.isa b/src/arch/riscv/isa/operands.isa
index 7c80b8acd50517afedf0a58f4e427d608a40b778..12f55778cc29cccc37712dfeb3cbdd7c68292995 100644 (file)
--- a/src/arch/riscv/isa/operands.isa
+++ b/src/arch/riscv/isa/operands.isa
@@ -2,6 +2,7 @@
 
 // Copyright (c) 2015 RISC-V Foundation
 // Copyright (c) 2016 The University of Virginia
+// Copyright (c) 2020 Barkhausen Institut
 // All rights reserved.
 //
 // Redistribution and use in source and binary forms, with or without
@@ -53,6 +54,8 @@ def operands {{
     'ra': ('IntReg', 'ud', 'ReturnAddrReg', 'IsInteger', 1),
     'sp': ('IntReg', 'ud', 'StackPointerReg', 'IsInteger', 2),
 
+    'a0': ('IntReg', 'ud', '10', 'IsInteger', 1),
+
     'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 1),
     'Fd_bits': ('FloatReg', 'ud', 'FD', 'IsFloating', 1),
     'Fs1': ('FloatReg', 'df', 'FS1', 'IsFloating', 2),

diff --git a/src/arch/riscv/utility.hh b/src/arch/riscv/utility.hh
index 7dcd5e2fd4ea9440aa44c974dcc0b258ad26feed..32eaff644349e1cc34e05db4ce26b0a4754b761a 100644 (file)
--- a/src/arch/riscv/utility.hh
+++ b/src/arch/riscv/utility.hh
@@ -2,6 +2,7 @@
  * Copyright (c) 2013 ARM Limited
  * Copyright (c) 2014-2015 Sven Karlsson
  * Copyright (c) 2018 TU Dresden
+ * Copyright (c) 2020 Barkhausen Institut
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -109,7 +110,14 @@ buildRetPC(const PCState &curPC, const PCState &callPC)
 inline uint64_t
 getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
 {
-    return 0;
+    panic_if(fp, "getArgument(): Floating point arguments not implemented");
+    panic_if(size != 8, "getArgument(): Can only handle 64-bit arguments.");
+    panic_if(number >= ArgumentRegs.size(),
+             "getArgument(): Don't know how to handle stack arguments");
+
+    // The first 8 integer arguments are passed in registers, the rest
+    // are passed on the stack.
+    return tc->readIntReg(ArgumentRegs[number]);
 }
 
 inline void