x86: Add a separate register for D flag bit

The D flag bit is part of the cc flag bit register currently. But since it
is not being used any where in the implementation, it creates an unnecessary
dependency. Hence, it is being moved to a separate register.

diff --git a/src/arch/x86/isa/microops/debug.isa b/src/arch/x86/isa/microops/debug.isa
index 2d6af83567a2c465fc6b2ba39f53ce04710d664e..b9da9c602539905b9ab8af314b33724f6cc79bc0 100644 (file)
--- a/src/arch/x86/isa/microops/debug.isa
+++ b/src/arch/x86/isa/microops/debug.isa
@@ -142,7 +142,7 @@ let {{
                  "func": func,
                  "func_num": "GenericISA::M5DebugFault::%s" % func_num,
                  "cond_test": "checkCondition(ccFlagBits | cfofBits | \
-                                              ecfBit | ezfBit, cc)"})
+                                              dfBit | ecfBit | ezfBit, cc)"})
         exec_output += MicroDebugExecute.subst(iop)
         header_output += MicroDebugDeclare.subst(iop)
         decoder_output += MicroDebugConstructor.subst(iop)

diff --git a/src/arch/x86/isa/microops/fpop.isa b/src/arch/x86/isa/microops/fpop.isa
index 08a74173cc735cf9544e8c1ec27c93feff6f4460..7acbe04eadff52441a3edcdc5692ff13a0e4099b 100644 (file)
--- a/src/arch/x86/isa/microops/fpop.isa
+++ b/src/arch/x86/isa/microops/fpop.isa
@@ -215,8 +215,8 @@ let {{
                     spm, SetStatus, dataSize)
         code = 'FpDestReg_uqw = FpSrcReg1_uqw;'
         else_code = 'FpDestReg_uqw = FpDestReg_uqw;'
-        cond_check = "checkCondition(ccFlagBits | cfofBits | ecfBit | ezfBit, \
-                                     src2)"
+        cond_check = "checkCondition(ccFlagBits | cfofBits | dfBit | \
+                                     ecfBit | ezfBit, src2)"
 
     class Xorfp(FpOp):
         code = 'FpDestReg_uqw = FpSrcReg1_uqw ^ FpSrcReg2_uqw;'

diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index cb1d577d7b963b856c0bb143be4c0fec5b49068a..a96a552a36d9d2f0f050ce31f09cdb45b99586ad 100644 (file)
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -438,9 +438,10 @@ let {{
         flag_code = '''
             //Don't have genFlags handle the OF or CF bits
             uint64_t mask = CFBit | ECFBit | OFBit;
-            uint64_t newFlags = genFlags(ccFlagBits | ezfBit, ext & ~mask,
-                                  result, psrc1, op2);
+            uint64_t newFlags = genFlags(ccFlagBits | dfBit | ezfBit,
+                                         ext & ~mask, result, psrc1, op2);
             ezfBit = newFlags & EZFBit;
+            dfBit = newFlags & DFBit;
             ccFlagBits = newFlags & ccFlagMask;
 
             //If a logic microop wants to set these, it wants to set them to 0.
@@ -451,29 +452,32 @@ let {{
     class FlagRegOp(RegOp):
         abstract = True
         flag_code = '''
-            uint64_t newFlags = genFlags(ccFlagBits | cfofBits | ecfBit |
-                                  ezfBit, ext, result, psrc1, op2);
+            uint64_t newFlags = genFlags(ccFlagBits | cfofBits | dfBit |
+                                    ecfBit | ezfBit, ext, result, psrc1, op2);
             cfofBits = newFlags & cfofMask;
             ecfBit = newFlags & ECFBit;
             ezfBit = newFlags & EZFBit;
+            dfBit = newFlags & DFBit;
             ccFlagBits = newFlags & ccFlagMask;
         '''
 
     class SubRegOp(RegOp):
         abstract = True
         flag_code = '''
-            uint64_t newFlags = genFlags(ccFlagBits | cfofBits | ecfBit |
-                                  ezfBit, ext, result, psrc1, ~op2, true);
+            uint64_t newFlags = genFlags(ccFlagBits | cfofBits | dfBit |
+                                         ecfBit | ezfBit, ext, result, psrc1,
+                                         ~op2, true);
             cfofBits = newFlags & cfofMask;
             ecfBit = newFlags & ECFBit;
             ezfBit = newFlags & EZFBit;
+            dfBit = newFlags & DFBit;
             ccFlagBits = newFlags & ccFlagMask;
         '''
 
     class CondRegOp(RegOp):
         abstract = True
-        cond_check = "checkCondition(ccFlagBits | cfofBits | ecfBit | ezfBit, \
-                                     ext)"
+        cond_check = "checkCondition(ccFlagBits | cfofBits | dfBit | ecfBit | \
+                                     ezfBit, ext)"
         cond_control_flag_init = "flags[IsCondControl] = flags[IsControl];"
 
     class RdRegOp(RegOp):
@@ -732,9 +736,10 @@ let {{
                     cfofBits = cfofBits | OFBit;
 
                 //Use the regular mechanisms to calculate the other flags.
-                uint64_t newFlags = genFlags(ccFlagBits | ezfBit,
+                uint64_t newFlags = genFlags(ccFlagBits | dfBit | ezfBit,
                         ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2);
                 ezfBit = newFlags & EZFBit;
+                dfBit = newFlags & DFBit;
                 ccFlagBits = newFlags & ccFlagMask;
             }
         '''
@@ -774,9 +779,10 @@ let {{
                     cfofBits = cfofBits | OFBit;
 
                 //Use the regular mechanisms to calculate the other flags.
-                uint64_t newFlags = genFlags(ccFlagBits | ezfBit,
+                uint64_t newFlags = genFlags(ccFlagBits | dfBit | ezfBit,
                         ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2);
                 ezfBit = newFlags & EZFBit;
+                dfBit = newFlags & DFBit;
                 ccFlagBits = newFlags & ccFlagMask;
             }
         '''
@@ -815,9 +821,10 @@ let {{
                 }
 
                 //Use the regular mechanisms to calculate the other flags.
-                uint64_t newFlags = genFlags(ccFlagBits | ezfBit,
+                uint64_t newFlags = genFlags(ccFlagBits | dfBit | ezfBit,
                         ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2);
                 ezfBit = newFlags & EZFBit;
+                dfBit = newFlags & DFBit;
                 ccFlagBits = newFlags & ccFlagMask;
             }
         '''
@@ -856,9 +863,10 @@ let {{
                     cfofBits = cfofBits | OFBit;
 
                 //Use the regular mechanisms to calculate the other flags.
-                uint64_t newFlags = genFlags(ccFlagBits | ezfBit,
+                uint64_t newFlags = genFlags(ccFlagBits | dfBit | ezfBit,
                         ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2);
                 ezfBit = newFlags & EZFBit;
+                dfBit = newFlags & DFBit;
                 ccFlagBits = newFlags & ccFlagMask;
             }
         '''
@@ -901,9 +909,10 @@ let {{
                 }
 
                 //Use the regular mechanisms to calculate the other flags.
-                uint64_t newFlags = genFlags(ccFlagBits | ezfBit,
+                uint64_t newFlags = genFlags(ccFlagBits | dfBit | ezfBit,
                     ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2);
                 ezfBit = newFlags & EZFBit;
+                dfBit = newFlags & DFBit;
                 ccFlagBits = newFlags & ccFlagMask;
             }
         '''
@@ -943,9 +952,10 @@ let {{
                     cfofBits = cfofBits | OFBit;
 
                 //Use the regular mechanisms to calculate the other flags.
-                uint64_t newFlags = genFlags(ccFlagBits | ezfBit,
+                uint64_t newFlags = genFlags(ccFlagBits | dfBit | ezfBit,
                     ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2);
                 ezfBit = newFlags & EZFBit;
+                dfBit = newFlags & DFBit;
                 ccFlagBits = newFlags & ccFlagMask;
             }
         '''
@@ -990,9 +1000,10 @@ let {{
                     cfofBits = cfofBits | OFBit;
 
                 //Use the regular mechanisms to calculate the other flags.
-                uint64_t newFlags = genFlags(ccFlagBits | ezfBit,
+                uint64_t newFlags = genFlags(ccFlagBits | dfBit | ezfBit,
                     ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2);
                 ezfBit = newFlags & EZFBit;
+                dfBit = newFlags & DFBit;
                 ccFlagBits = newFlags & ccFlagMask;
             }
         '''
@@ -1047,9 +1058,10 @@ let {{
                     cfofBits = cfofBits | OFBit;
 
                 //Use the regular mechanisms to calculate the other flags.
-                uint64_t newFlags = genFlags(ccFlagBits | ezfBit,
+                uint64_t newFlags = genFlags(ccFlagBits | dfBit | ezfBit,
                         ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2);
                 ezfBit = newFlags & EZFBit;
+                dfBit = newFlags & DFBit;
                 ccFlagBits = newFlags & ccFlagMask;
             }
         '''
@@ -1110,9 +1122,10 @@ let {{
                     cfofBits = cfofBits | OFBit;
 
                 //Use the regular mechanisms to calculate the other flags.
-                uint64_t newFlags = genFlags(ccFlagBits | ezfBit,
+                uint64_t newFlags = genFlags(ccFlagBits | dfBit | ezfBit,
                       ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2);
                 ezfBit = newFlags & EZFBit;
+                dfBit = newFlags & DFBit;
                 ccFlagBits = newFlags & ccFlagMask;
             }
         '''
@@ -1130,6 +1143,7 @@ let {{
             cfofBits = newFlags & cfofMask;
             ecfBit = newFlags & ECFBit;
             ezfBit = newFlags & EZFBit;
+            dfBit = newFlags & DFBit;
             ccFlagBits = newFlags & ccFlagMask;
         '''
 
@@ -1140,6 +1154,7 @@ let {{
 
             // Get only the user flags
             ccFlagBits = newFlags & ccFlagMask;
+            dfBit = newFlags & DFBit;
             cfofBits = newFlags & cfofMask;
             ecfBit = 0;
             ezfBit = 0;
@@ -1152,22 +1167,25 @@ let {{
         code = 'DestReg = NRIP - CSBase;'
 
     class Ruflags(RdRegOp):
-        code = 'DestReg = ccFlagBits | cfofBits | ecfBit | ezfBit;'
+        code = 'DestReg = ccFlagBits | cfofBits | dfBit | ecfBit | ezfBit;'
 
     class Rflags(RdRegOp):
         code = '''
-            DestReg = ccFlagBits | cfofBits | ecfBit | ezfBit | nccFlagBits;
+            DestReg = ccFlagBits | cfofBits | dfBit |
+                      ecfBit | ezfBit | nccFlagBits;
             '''
 
     class Ruflag(RegOp):
         code = '''
-            int flag = bits(ccFlagBits | cfofBits | ecfBit | ezfBit, imm8);
+            int flag = bits(ccFlagBits | cfofBits | dfBit |
+                            ecfBit | ezfBit, imm8);
             DestReg = merge(DestReg, flag, dataSize);
             ezfBit = (flag == 0) ? EZFBit : 0;
             '''
 
         big_code = '''
-            int flag = bits(ccFlagBits | cfofBits | ecfBit | ezfBit, imm8);
+            int flag = bits(ccFlagBits | cfofBits | dfBit |
+                            ecfBit | ezfBit, imm8);
             DestReg = flag & mask(dataSize * 8);
             ezfBit = (flag == 0) ? EZFBit : 0;
             '''
@@ -1180,7 +1198,7 @@ let {{
     class Rflag(RegOp):
         code = '''
             MiscReg flagMask = 0x3F7FDD5;
-            MiscReg flags = (nccFlagBits | ccFlagBits | cfofBits |
+            MiscReg flags = (nccFlagBits | ccFlagBits | cfofBits | dfBit |
                              ecfBit | ezfBit) & flagMask;
 
             int flag = bits(flags, imm8);
@@ -1190,7 +1208,7 @@ let {{
 
         big_code = '''
             MiscReg flagMask = 0x3F7FDD5;
-            MiscReg flags = (nccFlagBits | ccFlagBits | cfofBits |
+            MiscReg flags = (nccFlagBits | ccFlagBits | cfofBits | dfBit |
                              ecfBit | ezfBit) & flagMask;
 
             int flag = bits(flags, imm8);

diff --git a/src/arch/x86/isa/microops/seqop.isa b/src/arch/x86/isa/microops/seqop.isa
index e3b2511624ed735744a6eec3d6bc442b99c22811..d60ddced7f1d0b356ba6766d0b511fe428754af0 100644 (file)
--- a/src/arch/x86/isa/microops/seqop.isa
+++ b/src/arch/x86/isa/microops/seqop.isa
@@ -172,7 +172,7 @@ let {{
     iop = InstObjParams("br", "MicroBranchFlags", "SeqOpBase",
             {"code": "nuIP = target;",
              "else_code": "nuIP = nuIP;",
-             "cond_test": "checkCondition(ccFlagBits | cfofBits | \
+             "cond_test": "checkCondition(ccFlagBits | cfofBits | dfBit | \
                                           ecfBit | ezfBit, cc)",
              "cond_control_flag_init": "flags[IsCondControl] = true"})
     exec_output += SeqOpExecute.subst(iop)
@@ -190,7 +190,7 @@ let {{
 
     iop = InstObjParams("eret", "EretFlags", "SeqOpBase",
             {"code": "", "else_code": "",
-             "cond_test": "checkCondition(ccFlagBits | cfofBits | \
+             "cond_test": "checkCondition(ccFlagBits | cfofBits | dfBit | \
                                           ecfBit | ezfBit, cc)",
              "cond_control_flag_init": ""})
     exec_output += SeqOpExecute.subst(iop)

diff --git a/src/arch/x86/isa/microops/specop.isa b/src/arch/x86/isa/microops/specop.isa
index 8092b28b9aa7cc9ddb6fe21e7bcca255be50c73d..2f6bbd58dc3112fcbcb186382f61d40fc5338945 100644 (file)
--- a/src/arch/x86/isa/microops/specop.isa
+++ b/src/arch/x86/isa/microops/specop.isa
@@ -181,7 +181,7 @@ let {{
 
     iop = InstObjParams("fault", "MicroFaultFlags", "MicroFaultBase",
             {"code": "",
-             "cond_test": "checkCondition(ccFlagBits | cfofBits | \
+             "cond_test": "checkCondition(ccFlagBits | cfofBits | dfBit | \
                                           ecfBit | ezfBit, cc)"})
     exec_output = MicroFaultExecute.subst(iop)
     header_output = MicroFaultDeclare.subst(iop)

diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa
index 8e2ae7fd440f0c2b3d3c7529c72ba6c2d1f710a0..e0cd2d628c160ae1d1fbfee38f31b859b38180bb 100644 (file)
--- a/src/arch/x86/isa/operands.isa
+++ b/src/arch/x86/isa/operands.isa
@@ -120,12 +120,13 @@ def operands {{
         # nccFlagBits version holds the rest.
         'ccFlagBits':    intReg('INTREG_PSEUDO(0)', 60),
         'cfofBits':      intReg('INTREG_PSEUDO(1)', 61),
-        'ecfBit':        intReg('INTREG_PSEUDO(2)', 62),
-        'ezfBit':        intReg('INTREG_PSEUDO(3)', 63),
+        'dfBit':         intReg('INTREG_PSEUDO(2)', 62),
+        'ecfBit':        intReg('INTREG_PSEUDO(3)', 63),
+        'ezfBit':        intReg('INTREG_PSEUDO(4)', 64),
         # These register should needs to be more protected so that later
         # instructions don't map their indexes with an old value.
-        'nccFlagBits':   controlReg('MISCREG_RFLAGS', 64),
-        'TOP':           controlReg('MISCREG_X87_TOP', 65, ctype='ub'),
+        'nccFlagBits':   controlReg('MISCREG_RFLAGS', 65),
+        'TOP':           controlReg('MISCREG_X87_TOP', 66, ctype='ub'),
         # The segment base as used by memory instructions.
         'SegBase':       controlReg('MISCREG_SEG_EFF_BASE(segment)', 70),
 

diff --git a/src/arch/x86/regs/misc.hh b/src/arch/x86/regs/misc.hh
index bb69d8007a1941f829c40860ad8cc38dd3405a20..697c81fc93aeb30944331dfe4633022bf3a29bc5 100644 (file)
--- a/src/arch/x86/regs/misc.hh
+++ b/src/arch/x86/regs/misc.hh
@@ -65,7 +65,7 @@ namespace X86ISA
     };
 
     const uint32_t cfofMask = CFBit | OFBit;
-    const uint32_t ccFlagMask = PFBit | AFBit | ZFBit | SFBit | DFBit;
+    const uint32_t ccFlagMask = PFBit | AFBit | ZFBit | SFBit;
 
     enum RFLAGBit {
         TFBit = 1 << 8,

diff --git a/src/arch/x86/x86_traits.hh b/src/arch/x86/x86_traits.hh
index 6157cb30ba2bce00a6cedb662b317208c769103c..408fda1061f7b040b9932788580e3c0b9dc55fb8 100644 (file)
--- a/src/arch/x86/x86_traits.hh
+++ b/src/arch/x86/x86_traits.hh
@@ -46,7 +46,7 @@ namespace X86ISA
 {
     const int NumMicroIntRegs = 16;
 
-    const int NumPseudoIntRegs = 4;
+    const int NumPseudoIntRegs = 5;
     //1. The condition code bits of the rflags register.
     const int NumImplicitIntRegs = 6;
     //1. The lower part of the result of multiplication.