struct r600_context {
struct radeon *radeon;
+ struct radeon_winsys_cs *cs;
struct r600_range *range;
unsigned nblocks;
struct r600_block **blocks;
unsigned pm4_dirty_cdwords;
unsigned ctx_pm4_ndwords;
unsigned init_dwords;
- unsigned nreloc;
+
unsigned creloc;
struct r600_reloc *reloc;
struct radeon_bo **bo;
if (r)
goto out_err;
+ ctx->cs = radeon->ws->cs_create(radeon->ws);
+
/* allocate cs variables */
- ctx->nreloc = RADEON_CTX_MAX_PM4;
- ctx->reloc = calloc(ctx->nreloc, sizeof(struct r600_reloc));
- if (ctx->reloc == NULL) {
- r = -ENOMEM;
- goto out_err;
- }
- ctx->bo = calloc(ctx->nreloc, sizeof(void *));
+ ctx->bo = calloc(RADEON_CTX_MAX_PM4, sizeof(void *));
if (ctx->bo == NULL) {
r = -ENOMEM;
goto out_err;
if (draw->indices) {
ndwords = 11;
- /* make sure there is enough relocation space before scheduling draw */
- if (ctx->creloc >= (ctx->nreloc - 1)) {
- r600_context_flush(ctx);
- }
}
/* queries need some special values */
r600_free_resource_range(ctx, &ctx->fs_resources, ctx->num_fs_resources);
free(ctx->range);
free(ctx->blocks);
- free(ctx->reloc);
free(ctx->bo);
free(ctx->pm4);
+ ctx->radeon->ws->cs_destroy(ctx->cs);
memset(ctx, 0, sizeof(struct r600_context));
}
if (r)
goto out_err;
+ ctx->cs = radeon->ws->cs_create(radeon->ws);
+
/* allocate cs variables */
- ctx->nreloc = RADEON_CTX_MAX_PM4;
- ctx->reloc = calloc(ctx->nreloc, sizeof(struct r600_reloc));
- if (ctx->reloc == NULL) {
- r = -ENOMEM;
- goto out_err;
- }
- ctx->bo = calloc(ctx->nreloc, sizeof(void *));
+ ctx->bo = calloc(RADEON_CTX_MAX_PM4, sizeof(void *));
if (ctx->bo == NULL) {
r = -ENOMEM;
goto out_err;
void r600_context_get_reloc(struct r600_context *ctx, struct r600_bo *rbo)
{
struct radeon_bo *bo = rbo->bo;
- bo->reloc = &ctx->reloc[ctx->creloc];
- bo->reloc_id = ctx->creloc * sizeof(struct r600_reloc) / 4;
- ctx->reloc[ctx->creloc].handle = bo->handle;
- ctx->reloc[ctx->creloc].read_domain = rbo->domains & (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM);
- ctx->reloc[ctx->creloc].write_domain = rbo->domains & (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM);
- ctx->reloc[ctx->creloc].flags = 0;
- radeon_bo_reference(ctx->radeon, &ctx->bo[ctx->creloc], bo);
- ctx->creloc++;
+
+ unsigned reloc_index = ctx->radeon->ws->trans_add_reloc(ctx->cs, bo->cs_buf,
+ rbo->domains & (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM),
+ rbo->domains & (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM),
+ (void**)&ctx->reloc, &ctx->creloc);
+
+ bo->reloc = (void*)1;
+ bo->reloc_id = reloc_index * 4;
+ radeon_bo_reference(ctx->radeon, &ctx->bo[reloc_index], bo);
}
void r600_context_reg(struct r600_context *ctx,
if (draw->indices) {
ndwords = 11;
- /* make sure there is enough relocation space before scheduling draw */
- if (ctx->creloc >= (ctx->nreloc - 1)) {
- r600_context_flush(ctx);
- }
}
/* queries need some special values */
ctx->pm4_dirty_cdwords = 0;
ctx->pm4_cdwords = 0;
ctx->flags = 0;
+ ctx->radeon->ws->cs_flush(ctx->cs, 0);
r600_init_cs(ctx);
{
unsigned ndwords = 10;
- if (((ctx->pm4_dirty_cdwords + ndwords + ctx->pm4_cdwords) > ctx->pm4_ndwords) ||
- (ctx->creloc >= (ctx->nreloc - 1))) {
+ if ((ctx->pm4_dirty_cdwords + ndwords + ctx->pm4_cdwords) > ctx->pm4_ndwords) {
/* need to flush */
r600_context_flush(ctx);
}
struct radeon_bo {
struct pipe_reference reference;
struct pb_buffer *buf;
+ struct radeon_winsys_cs_handle *cs_buf;
unsigned handle;
unsigned size;
int map_count;
FREE(bo);
return NULL;
}
+ bo->cs_buf = radeon->ws->buffer_get_cs_handle(bo->buf);
bo->handle = radeon->ws->trans_get_buffer_handle(bo->buf);
bo->size = size;
return bo;
return -1;
}
-static void radeon_add_reloc(struct radeon_cs_context *csc,
- struct radeon_bo *bo,
- enum radeon_bo_domain rd,
- enum radeon_bo_domain wd,
- enum radeon_bo_domain *added_domains)
+static unsigned radeon_add_reloc(struct radeon_cs_context *csc,
+ struct radeon_bo *bo,
+ enum radeon_bo_domain rd,
+ enum radeon_bo_domain wd,
+ enum radeon_bo_domain *added_domains)
{
struct drm_radeon_cs_reloc *reloc;
unsigned i;
reloc = csc->relocs_hashlist[hash];
if (reloc->handle == bo->handle) {
update_domains(reloc, rd, wd, added_domains);
- return;
+ return csc->reloc_indices_hashlist[hash];
}
/* Hash collision, look for the BO in the list of relocs linearly. */
csc->relocs_hashlist[hash] = reloc;
csc->reloc_indices_hashlist[hash] = i;
/*printf("write_reloc collision, hash: %i, handle: %i\n", hash, bo->handle);*/
- return;
+ return i;
}
}
}
csc->reloc_indices_hashlist[hash] = csc->crelocs;
csc->chunks[1].length_dw += RELOC_DWORDS;
- csc->crelocs++;
*added_domains = rd | wd;
+ return csc->crelocs++;
}
static void radeon_drm_cs_add_reloc(struct radeon_winsys_cs *rcs,
return radeon_bo_is_referenced_by_cs(cs, bo);
}
+static unsigned trans_add_reloc(struct radeon_winsys_cs *rcs,
+ struct radeon_winsys_cs_handle *buf,
+ enum radeon_bo_domain rd,
+ enum radeon_bo_domain wd,
+ void **reloc_list, unsigned *reloc_count)
+{
+ struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
+ struct radeon_bo *bo = (struct radeon_bo*)buf;
+ enum radeon_bo_domain added_domains;
+
+ unsigned index = radeon_add_reloc(cs->csc, bo, rd, wd, &added_domains);
+
+ if (added_domains & RADEON_DOMAIN_GTT)
+ cs->csc->used_gart += bo->size;
+ if (added_domains & RADEON_DOMAIN_VRAM)
+ cs->csc->used_vram += bo->size;
+
+ *reloc_list = cs->csc->relocs;
+ *reloc_count = cs->csc->crelocs;
+ return index;
+}
+
void radeon_drm_cs_init_functions(struct radeon_drm_winsys *ws)
{
ws->base.cs_create = radeon_drm_cs_create;
ws->base.cs_flush = radeon_drm_cs_flush;
ws->base.cs_set_flush = radeon_drm_cs_set_flush;
ws->base.cs_is_buffer_referenced = radeon_bo_is_referenced;
+
+ ws->base.trans_add_reloc = trans_add_reloc;
}
/* Transitional functions for r600g when moving to winsys/radeon */
unsigned (*trans_get_buffer_handle)(struct pb_buffer *buf);
+ unsigned (*trans_add_reloc)(struct radeon_winsys_cs *cs,
+ struct radeon_winsys_cs_handle *buf,
+ enum radeon_bo_domain rd,
+ enum radeon_bo_domain wd,
+ void **reloc_list, unsigned *reloc_count);
};
#endif