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Added english language description, spaces and brackets for lhz instruction
author
Shriya Sharma
<shriya@redsemiconductor.com>
Tue, 26 Sep 2023 10:20:28 +0000
(11:20 +0100)
committer
Shriya Sharma
<shriya@redsemiconductor.com>
Tue, 26 Sep 2023 10:20:28 +0000
(11:20 +0100)
openpower/isa/fixedload.mdwn
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diff --git
a/openpower/isa/fixedload.mdwn
b/openpower/isa/fixedload.mdwn
index 8d684f861276b347a93649ec3d57ca5e69cb4fd7..8ab40cb3505dc3ef085559fca9c32aa4024ffc60 100644
(file)
--- a/
openpower/isa/fixedload.mdwn
+++ b/
openpower/isa/fixedload.mdwn
@@
-134,6
+134,12
@@
Pseudo-code:
EA <- b + EXTS(D)
RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
+Description:
+
+ Let the effective address (EA) be the sum (RA|0)+ D.
+ The halfword in storage addressed by EA is loaded into
+ RT[48:63]. RT[0:47] are set to 0.
+
Special Registers Altered:
None