i965: Move up fs_inst::regs_written to backend_instruction.
authorFrancisco Jerez <currojerez@riseup.net>
Thu, 5 Feb 2015 23:27:40 +0000 (01:27 +0200)
committerFrancisco Jerez <currojerez@riseup.net>
Tue, 10 Feb 2015 14:05:51 +0000 (16:05 +0200)
It will also be useful in the VEC4 back-end.

Reviewed-by: Matt Turner <mattst88@gmail.com>
src/mesa/drivers/dri/i965/brw_ir_fs.h
src/mesa/drivers/dri/i965/brw_shader.h
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp

index 6ce2e017a9ab6f20565b67e4ff8b0ef9197203b5..a85adaebe99ed289db24f8ecdd5da0e85af7b708 100644 (file)
@@ -244,7 +244,6 @@ public:
     */
    uint8_t flag_subreg;
 
-   uint8_t regs_written; /**< Number of vgrfs written by a SEND message, or 1 */
    bool eot:1;
    bool force_uncompressed:1;
    bool force_sechalf:1;
index ab3ad60e02b2927ce82ca32adb453e231ab4e999..00bb4905c4c40ec8f5e09dcddea6d1c8b442f09c 100644 (file)
@@ -122,6 +122,7 @@ struct backend_instruction {
    uint8_t mlen; /**< SEND message length */
    int8_t base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
    uint8_t target; /**< MRT target. */
+   uint8_t regs_written; /**< Number of registers written by the instruction. */
 
    enum opcode opcode; /* BRW_OPCODE_* or FS_OPCODE_* */
    enum brw_conditional_mod conditional_mod; /**< BRW_CONDITIONAL_* */
index 041c618fa430351f95535eb1f9e5662211921f7b..ada4a0cdc4d98f92aeffa1c879c1f7f65affdf78 100644 (file)
@@ -44,6 +44,7 @@ vec4_instruction::vec4_instruction(enum opcode opcode, const dst_reg &dst,
    this->writes_accumulator = false;
    this->conditional_mod = BRW_CONDITIONAL_NONE;
    this->target = 0;
+   this->regs_written = (dst.file == BAD_FILE ? 0 : 1);
    this->shadow_compare = false;
    this->ir = NULL;
    this->urb_write_flags = BRW_URB_WRITE_NO_FLAGS;