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arch-arm: TlbEntry flush to be considered as functional lookup
author
Giacomo Travaglini
<giacomo.travaglini@arm.com>
Tue, 15 Sep 2020 16:18:52 +0000
(17:18 +0100)
committer
Giacomo Travaglini
<giacomo.travaglini@arm.com>
Tue, 3 Nov 2020 09:55:11 +0000
(09:55 +0000)
Otherwise we are unnecessarily shifting the TLB entry to the
MRU position before invalidating it
Change-Id: I43ee04cd5267829ab7357f4fe1ff745023adc598
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35244
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
src/arch/arm/tlb.cc
patch
|
blob
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history
diff --git
a/src/arch/arm/tlb.cc
b/src/arch/arm/tlb.cc
index bad16d83b2cb5a67022de1ceb50a4f7a9a4fb6df..04b5cd409bbe6806232b1ae028ec00cdf8778e94 100644
(file)
--- a/
src/arch/arm/tlb.cc
+++ b/
src/arch/arm/tlb.cc
@@
-446,7
+446,7
@@
TLB::_flushMva(Addr mva, uint64_t asn, bool secure_lookup,
bool hyp = target_el == EL2;
- te = lookup(mva, asn, vmid, hyp, secure_lookup,
fals
e, ignore_asn,
+ te = lookup(mva, asn, vmid, hyp, secure_lookup,
tru
e, ignore_asn,
target_el, in_host);
while (te != NULL) {
if (secure_lookup == !te->nstid) {
@@
-454,7
+454,7
@@
TLB::_flushMva(Addr mva, uint64_t asn, bool secure_lookup,
te->valid = false;
stats.flushedEntries++;
}
- te = lookup(mva, asn, vmid, hyp, secure_lookup,
fals
e, ignore_asn,
+ te = lookup(mva, asn, vmid, hyp, secure_lookup,
tru
e, ignore_asn,
target_el, in_host);
}
}