soc_core: fix cpu_type=None case and add test for it

diff --git a/litex/soc/cores/cpu/__init__.py b/litex/soc/cores/cpu/__init__.py
index ec57b0b23de02f01ed5f948113487138ecb25616..b8d6aad2fa654f8fbab12da0cf6e16d4d1be9b14 100644 (file)
--- a/litex/soc/cores/cpu/__init__.py
+++ b/litex/soc/cores/cpu/__init__.py
@@ -18,6 +18,10 @@ class CPU(Module):
     interrupts           = {}
     mem_map              = {}
 
+class CPUNone(CPU):
+    data_width           = 32
+    reset_address        = 0x00000000
+
 # CPUS ---------------------------------------------------------------------------------------------
 
 from litex.soc.cores.cpu.lm32 import LM32

diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 85c6403ce13511c86e65f8cbc2c39a5cfabf27aa..b3f1ae4003fdc61c5b49e5a1306dc23e236dc909 100644 (file)
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -193,6 +193,8 @@ class SoCCore(Module):
             # Allow SoCController to reset the CPU
             if with_ctrl:
                 self.comb += self.cpu.reset.eq(self.ctrl.reset)
+        else:
+            self.add_cpu(cpu.CPUNone())
 
         # Add user's interrupts (needs to be done after CPU interrupts are allocated)
         for _name, _id in self.interrupt_map.items():

diff --git a/test/test_targets.py b/test/test_targets.py
index 157481e7721b85c7b392dabd09ba63db62db19ba..038faedb2bfe676a583e18c9b41e8b5b86d49c40 100644 (file)
--- a/test/test_targets.py
+++ b/test/test_targets.py
@@ -121,6 +121,11 @@ litex/boards/targets/simple.py litex.boards.platforms.{p} \
 """.format(p=p)
                 subprocess.check_call(cmd, shell=True)
 
+    def test_cpu_none(self):
+        from litex.boards.targets.arty import BaseSoC
+        errors = build_test([BaseSoC(cpu_type=None)])
+        self.assertEqual(errors, 0)
+
     def run_variants(self, cpu, variants):
         for v in variants:
             with self.subTest(cpu=cpu, variant=v):