r600/shader: handle bitfield extract semantics properly.

Fixes:
tests/spec/arb_gpu_shader5/execution/built-in-functions/fs-bitfieldExtract.shader_test

Signed-off-by: Dave Airlie <airlied@redhat.com>

diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 3a0ca34a4ccf1d235c3a93bd289b64eb5311a79d..0fa2a1f0d1ac505c2ec7b28d7109f335a4f1e0d0 100644 (file)
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -9107,6 +9107,55 @@ static int tgsi_up2h(struct r600_shader_ctx *ctx)
        return 0;
 }
 
+static int tgsi_bfe(struct r600_shader_ctx *ctx)
+{
+       struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
+       struct r600_bytecode_alu alu;
+       int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
+       int r, i;
+
+       r = tgsi_op3(ctx);
+       if (r)
+               return r;
+
+       for (i = 0; i < lasti + 1; i++) {
+               memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+               alu.op = ALU_OP2_SETGE_INT;
+               r600_bytecode_src(&alu.src[0], &ctx->src[2], i);
+               alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
+               alu.src[1].value = 32;
+               alu.dst.sel = ctx->temp_reg;
+               alu.dst.chan = i;
+               alu.dst.write = 1;
+               if (i == lasti)
+                       alu.last = 1;
+               r = r600_bytecode_add_alu(ctx->bc, &alu);
+               if (r)
+                       return r;
+       }
+
+       for (i = 0; i < lasti + 1; i++) {
+               memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+               alu.op = ALU_OP3_CNDE_INT;
+               alu.is_op3 = 1;
+               alu.src[0].sel = ctx->temp_reg;
+               alu.src[1].chan = i;
+
+               tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
+               alu.src[1].sel = alu.dst.sel;
+               alu.src[1].chan = i;
+               r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
+               alu.dst.write = 1;
+               if (i == lasti)
+                       alu.last = 1;
+               r = r600_bytecode_add_alu(ctx->bc, &alu);
+               if (r)
+                       return r;
+       }
+
+       return 0;
+}
+
 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
        [TGSI_OPCODE_ARL]       = { ALU_OP0_NOP, tgsi_r600_arl},
        [TGSI_OPCODE_MOV]       = { ALU_OP1_MOV, tgsi_op2},
@@ -9495,8 +9544,8 @@ static const struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] =
        [TGSI_OPCODE_UMUL_HI]   = { ALU_OP2_MULHI_UINT, tgsi_op2_trans},
        [TGSI_OPCODE_TG4]       = { FETCH_OP_GATHER4, tgsi_tex},
        [TGSI_OPCODE_LODQ]      = { FETCH_OP_GET_LOD, tgsi_tex},
-       [TGSI_OPCODE_IBFE]      = { ALU_OP3_BFE_INT, tgsi_op3},
-       [TGSI_OPCODE_UBFE]      = { ALU_OP3_BFE_UINT, tgsi_op3},
+       [TGSI_OPCODE_IBFE]      = { ALU_OP3_BFE_INT, tgsi_bfe},
+       [TGSI_OPCODE_UBFE]      = { ALU_OP3_BFE_UINT, tgsi_bfe},
        [TGSI_OPCODE_BFI]       = { ALU_OP0_NOP, tgsi_bfi},
        [TGSI_OPCODE_BREV]      = { ALU_OP1_BFREV_INT, tgsi_op2},
        [TGSI_OPCODE_POPC]      = { ALU_OP1_BCNT_INT, tgsi_op2},
@@ -9718,8 +9767,8 @@ static const struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] =
        [TGSI_OPCODE_UMUL_HI]   = { ALU_OP2_MULHI_UINT, cayman_mul_int_instr},
        [TGSI_OPCODE_TG4]       = { FETCH_OP_GATHER4, tgsi_tex},
        [TGSI_OPCODE_LODQ]      = { FETCH_OP_GET_LOD, tgsi_tex},
-       [TGSI_OPCODE_IBFE]      = { ALU_OP3_BFE_INT, tgsi_op3},
-       [TGSI_OPCODE_UBFE]      = { ALU_OP3_BFE_UINT, tgsi_op3},
+       [TGSI_OPCODE_IBFE]      = { ALU_OP3_BFE_INT, tgsi_bfe},
+       [TGSI_OPCODE_UBFE]      = { ALU_OP3_BFE_UINT, tgsi_bfe},
        [TGSI_OPCODE_BFI]       = { ALU_OP0_NOP, tgsi_bfi},
        [TGSI_OPCODE_BREV]      = { ALU_OP1_BFREV_INT, tgsi_op2},
        [TGSI_OPCODE_POPC]      = { ALU_OP1_BCNT_INT, tgsi_op2},