}
void
-fs_visitor::dump_instruction(fs_inst *inst)
+fs_visitor::dump_instruction(backend_instruction *be_inst)
{
+ fs_inst *inst = (fs_inst *)be_inst;
+
if (inst->predicate) {
printf("(%cf0.%d) ",
inst->predicate_inverse ? '-' : '+',
printf("\n");
}
-void
-fs_visitor::dump_instructions()
-{
- int ip = 0;
- foreach_list(node, &this->instructions) {
- fs_inst *inst = (fs_inst *)node;
- printf("%d: ", ip++);
- dump_instruction(inst);
- }
-}
-
/**
* Possibly returns an instruction that set up @param reg.
*
void setup_builtin_uniform_values(ir_variable *ir);
int implied_mrf_writes(fs_inst *inst);
- void dump_instructions();
- void dump_instruction(fs_inst *inst);
+ void dump_instruction(backend_instruction *inst);
struct gl_fragment_program *fp;
struct brw_wm_compile *c;
return false;
}
}
+
+void
+backend_visitor::dump_instructions()
+{
+ int ip = 0;
+ foreach_list(node, &this->instructions) {
+ backend_instruction *inst = (backend_instruction *)node;
+ printf("%d: ", ip++);
+ dump_instruction(inst);
+ }
+}
* backend_instruction)
*/
exec_list instructions;
+
+ virtual void dump_instruction(backend_instruction *inst) = 0;
+ void dump_instructions();
};
int brw_type_for_base_type(const struct glsl_type *type);
}
void
-vec4_visitor::dump_instruction(vec4_instruction *inst)
+vec4_visitor::dump_instruction(backend_instruction *be_inst)
{
+ vec4_instruction *inst = (vec4_instruction *)be_inst;
+
printf("%s ", brw_instruction_name(inst->opcode));
switch (inst->dst.file) {
printf("\n");
}
-void
-vec4_visitor::dump_instructions()
-{
- int ip = 0;
- foreach_list_safe(node, &this->instructions) {
- vec4_instruction *inst = (vec4_instruction *)node;
- printf("%d: ", ip++);
- dump_instruction(inst);
- }
-}
-
/**
* Replace each register of type ATTR in this->instructions with a reference
* to a fixed HW register.
bool process_move_condition(ir_rvalue *ir);
- void dump_instruction(vec4_instruction *inst);
- void dump_instructions();
+ void dump_instruction(backend_instruction *inst);
protected:
void emit_vertex();