(no commit message)

diff --git a/openpower/sv/biginteger.mdwn b/openpower/sv/biginteger.mdwn
index a1be1ccb3aa94cbc7e248b59b687cc1abd77c407..ec4b4636c70d8fe965cbbbb084668da0c81c3c85 100644 (file)
--- a/openpower/sv/biginteger.mdwn
+++ b/openpower/sv/biginteger.mdwn
@@ -191,7 +191,8 @@ used with the additional bit set for determining RS.
 | EXTRA2_MODE   | `18`    | used by `msubed` and `madded` for RS   |
 
 When `EXTRA2_MODE` is set to zero, the implicit RS register takes
-its Vector/Scalar setting from Rdest_EXTRA2, but all numbering
+its Vector/Scalar setting from Rdest_EXTRA2, and takes
+the register number from RT, but all numbering
 is offset by VL. *Note that element-width overrides influence this
 offset* (see SVP64 [[svp64/appendix]] for full details).