+2017-07-02 Richard Earnshaw <rearnsha@arm.com>
+
+ * common/config/arm/arm-common.c (arm_be8_option): New function.
+ * config/arm/arm-isa.h (isa_feature): Add new feature bit isa_bit_be8.
+ (ISA_ARMv6): Add isa_bit_be8.
+ * config/arm/arm.h (arm_be8_option): Add prototype.
+ (BE8_SPEC_FUNCTION): New define.
+ (EXTRA_SPEC_FUNCTIONS): Add BE8_SPEC_FUNCTION.
+ * config/arm/arm.opt (mbig-endian): Mark as Negative of mlittle-endian.
+ (mlittle-endian): Similarly.
+ (mbe8, mbe32): New options.
+ * config/arm/bpabi.h (BE8_LINK_SPEC): Call arm_be8_option.
+ * doc/invoke.texi (ARM Options): Document -mbe8 and -mbe32.
+
2017-07-02 Jan Hubicka <hubicka@ucw.cz>
* tree-cfg.c (gimple_find_sub_bbs): Fix profile updating.
return canonical_arch;
}
+/* If building big-endian on a BE8 target generate a --be8 option for
+ the linker. Takes four types of option: "little" - little-endian;
+ "big" - big-endian; "be8" - force be8 iff big-endian; and "arch"
+ "<arch-name>" (two arguments) - the target architecture. The
+ parameter names are generated by the driver from the command-line
+ options. */
+const char *
+arm_be8_option (int argc, const char **argv)
+{
+ int endian = TARGET_ENDIAN_DEFAULT;
+ const char *arch = NULL;
+ int arg;
+ bool force = false;
+
+ for (arg = 0; arg < argc; arg++)
+ {
+ if (strcmp (argv[arg], "little") == 0)
+ endian = 0;
+ else if (strcmp (argv[arg], "big") == 0)
+ endian = 1;
+ else if (strcmp (argv[arg], "be8") == 0)
+ force = true;
+ else if (strcmp (argv[arg], "arch") == 0)
+ {
+ arg++;
+ gcc_assert (arg < argc);
+ arch = argv[arg];
+ }
+ else
+ gcc_unreachable ();
+ }
+
+ /* Little endian - no be8 option. */
+ if (!endian)
+ return "";
+
+ if (force)
+ return "--be8";
+
+ /* Arch might not be set iff arm_canon_arch (above) detected an
+ error. Do nothing in that case. */
+ if (!arch)
+ return "";
+
+ const arch_option *selected_arch
+ = arm_parse_arch_option_name (all_architectures, "-march", arch);
+
+ /* Similarly if the given arch option was itself invalid. */
+ if (!selected_arch)
+ return "";
+
+ if (check_isa_bits_for (selected_arch->common.isa_bits, isa_bit_be8))
+ return "--be8";
+
+ return "";
+}
+
#undef ARM_CPU_NAME_LENGTH
isa_bit_ARMv6, /* Architecture rel 6. */
isa_bit_ARMv6k, /* Architecture rel 6k. */
isa_bit_thumb2, /* Thumb-2. */
- isa_bit_notm, /* Instructions that are not present in 'M' profile. */
+ isa_bit_notm, /* Instructions not present in 'M' profile. */
+ isa_bit_be8, /* Architecture uses be8 mode in big-endian. */
isa_bit_tdiv, /* Thumb division instructions. */
isa_bit_ARMv7em, /* Architecture rel 7e-m. */
isa_bit_ARMv7, /* Architecture rel 7. */
#define ISA_ARMv5e ISA_ARMv5, isa_bit_ARMv5e
#define ISA_ARMv5te ISA_ARMv5e, isa_bit_thumb
#define ISA_ARMv5tej ISA_ARMv5te
-#define ISA_ARMv6 ISA_ARMv5te, isa_bit_ARMv6
+#define ISA_ARMv6 ISA_ARMv5te, isa_bit_ARMv6, isa_bit_be8
#define ISA_ARMv6j ISA_ARMv6
#define ISA_ARMv6k ISA_ARMv6, isa_bit_ARMv6k
#define ISA_ARMv6z ISA_ARMv6
#define CANON_ARCH_SPEC_FUNCTION \
{ "canon_arch", arm_canon_arch_option },
+const char *arm_be8_option (int argc, const char **argv);
+#define BE8_SPEC_FUNCTION \
+ { "be8_linkopt", arm_be8_option },
+
# define EXTRA_SPEC_FUNCTIONS \
MCPU_MTUNE_NATIVE_FUNCTIONS \
ASM_CPU_SPEC_FUNCTIONS \
CANON_ARCH_SPEC_FUNCTION \
- TARGET_MODE_SPEC_FUNCTIONS
+ TARGET_MODE_SPEC_FUNCTIONS \
+ BE8_SPEC_FUNCTION
/* Automatically add -mthumb for Thumb-only targets if mode isn't specified
via the configuration option --with-mode or via the command line. The
Generate code in 32 bit ARM state.
mbig-endian
-Target Report RejectNegative Mask(BIG_END)
+Target Report RejectNegative Negative(mlittle-endian) Mask(BIG_END)
Assume target CPU is configured as big endian.
mcallee-super-interworking
Target RejectNegative Alias(mfloat-abi=, hard) Undocumented
mlittle-endian
-Target Report RejectNegative InverseMask(BIG_END)
+Target Report RejectNegative Negative(mbig-endian) InverseMask(BIG_END)
Assume target CPU is configured as little endian.
mlong-calls
mpure-code
Target Report Var(target_pure_code) Init(0)
Do not allow constant data to be placed in code sections.
+
+mbe8
+Target Report RejectNegative Negative(mbe32) Mask(BE8)
+When linking for big-endian targets, generate a BE8 format image.
+
+mbe32
+Target Report RejectNegative Negative(mbe8) InverseMask(BE8)
+When linking for big-endian targets, generate a legacy BE32 format image.
/* Use the AAPCS ABI by default. */
#define ARM_DEFAULT_ABI ARM_ABI_AAPCS
-/* Assume that AAPCS ABIs should adhere to the full BPABI. */
+/* Assume that AAPCS ABIs should adhere to the full BPABI. */
#define TARGET_BPABI (TARGET_AAPCS_BASED)
/* BPABI targets use EABI frame unwinding tables. */
#define TARGET_FIX_V4BX_SPEC " %{mcpu=arm8|mcpu=arm810|mcpu=strongarm*"\
"|march=armv4|mcpu=fa526|mcpu=fa626:--fix-v4bx}"
-#if TARGET_BIG_ENDIAN_DEFAULT
-#define BE8_LINK_SPEC \
- " %{!mlittle-endian:%{march=armv7-a|mcpu=cortex-a5 \
- |mcpu=cortex-a7 \
- |mcpu=cortex-a8|mcpu=cortex-a9|mcpu=cortex-a15 \
- |mcpu=cortex-a12|mcpu=cortex-a17 \
- |mcpu=cortex-a15.cortex-a7 \
- |mcpu=cortex-a17.cortex-a7 \
- |mcpu=marvell-pj4 \
- |mcpu=cortex-a32 \
- |mcpu=cortex-a35 \
- |mcpu=cortex-a53 \
- |mcpu=cortex-a57 \
- |mcpu=cortex-a57.cortex-a53 \
- |mcpu=cortex-a72 \
- |mcpu=cortex-a72.cortex-a53 \
- |mcpu=cortex-a73 \
- |mcpu=cortex-a73.cortex-a35 \
- |mcpu=cortex-a73.cortex-a53 \
- |mcpu=exynos-m1 \
- |mcpu=xgene1 \
- |mcpu=cortex-m1.small-multiply \
- |mcpu=cortex-m0.small-multiply \
- |mcpu=cortex-m0plus.small-multiply \
- |mcpu=generic-armv7-a \
- |march=armv7ve \
- |march=armv7-m|mcpu=cortex-m3 \
- |march=armv7e-m|mcpu=cortex-m4|mcpu=cortex-m7 \
- |march=armv6-m|mcpu=cortex-m0 \
- |march=armv8-a \
- |march=armv8-a+crc \
- |march=armv8.1-a \
- |march=armv8.1-a+crc \
- |march=armv8.2-a \
- |march=armv8.2-a+fp16 \
- |march=armv8-m.base|mcpu=cortex-m23 \
- |march=armv8-m.main \
- |march=armv8-m.main+dsp|mcpu=cortex-m33 \
- :%{!r:--be8}}}"
-#else
-#define BE8_LINK_SPEC \
- " %{mbig-endian:%{march=armv7-a|mcpu=cortex-a5 \
- |mcpu=cortex-a7 \
- |mcpu=cortex-a8|mcpu=cortex-a9|mcpu=cortex-a15 \
- |mcpu=cortex-a12|mcpu=cortex-a17 \
- |mcpu=cortex-a15.cortex-a7 \
- |mcpu=cortex-a17.cortex-a7 \
- |mcpu=cortex-a35 \
- |mcpu=cortex-a53 \
- |mcpu=cortex-a57 \
- |mcpu=cortex-a57.cortex-a53 \
- |mcpu=cortex-a72 \
- |mcpu=cortex-a72.cortex-a53 \
- |mcpu=cortex-a73 \
- |mcpu=cortex-a73.cortex-a35 \
- |mcpu=cortex-a73.cortex-a53 \
- |mcpu=exynos-m1 \
- |mcpu=xgene1 \
- |mcpu=cortex-m1.small-multiply \
- |mcpu=cortex-m0.small-multiply \
- |mcpu=cortex-m0plus.small-multiply \
- |mcpu=marvell-pj4 \
- |mcpu=generic-armv7-a \
- |march=armv7ve \
- |march=armv7-m|mcpu=cortex-m3 \
- |march=armv7e-m|mcpu=cortex-m4|mcpu=cortex-m7 \
- |march=armv6-m|mcpu=cortex-m0 \
- |march=armv8-a \
- |march=armv8-a+crc \
- |march=armv8.1-a \
- |march=armv8.1-a+crc \
- |march=armv8.2-a \
- |march=armv8.2-a+fp16 \
- |march=armv8-m.base|mcpu=cortex-m23 \
- |march=armv8-m.main \
- |march=armv8-m.main+dsp|mcpu=cortex-m33 \
- :%{!r:--be8}}}"
-#endif
+#define BE8_LINK_SPEC \
+ "%{!r:%{!mbe32:%:be8_linkopt(%{mlittle-endian:little}" \
+ " %{mbig-endian:big}" \
+ " %{mbe8:be8}" \
+ " %{march=*:arch %*})}}"
/* Tell the assembler to build BPABI binaries. */
#undef SUBTARGET_EXTRA_ASM_SPEC
Generate code for a processor running in big-endian mode; the default is
to compile code for a little-endian processor.
+@item -mbe8
+@itemx -mbe32
+@opindex mbe8
+When linking a big-endian image select between BE8 and BE32 formats.
+The option has no effect for little-endian images and is ignored. The
+default is dependent on the selected target architecture. For ARMv6
+and later architectures the default is BE8, for older architectures
+the default is BE32. BE32 format has been deprecated by ARM.
+
@item -march=@var{name@r{[}+extension@dots{}@r{]}}
@opindex march
This specifies the name of the target ARM architecture. GCC uses this
projects / gcc.git / commitdiff