#define M5OP_WORK_BEGIN 0x5a
#define M5OP_WORK_END 0x5b
-#define M5OP_SE_PAGE_FAULT 0x61
#define M5OP_DIST_TOGGLE_SYNC 0x62
#define M5OP_WORKLOAD 0x70
M5OP(m5_panic, M5OP_PANIC) \
M5OP(m5_work_begin, M5OP_WORK_BEGIN) \
M5OP(m5_work_end, M5OP_WORK_END) \
- M5OP(m5_se_page_fault, M5OP_SE_PAGE_FAULT) \
M5OP(m5_dist_toggle_sync, M5OP_DIST_TOGGLE_SYNC) \
M5OP(m5_workload, M5OP_WORKLOAD) \
void m5_work_begin(uint64_t workid, uint64_t threadid);
void m5_work_end(uint64_t workid, uint64_t threadid);
-void m5_se_page_fault();
-
/*
* Send a very generic poke to the workload so it can do something. It's up to
* the workload to know what information to look for to interpret an event,
isa.hh
isa_traits.hh
locked_mem.hh
- pseudo_inst.hh
registers.hh
remote_gdb.hh
types.hh
+++ /dev/null
-/*
- * Copyright (c) 2014 Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __ARCH_ARM_PSEUDO_INST_HH__
-#define __ARCH_ARM_PSEUDO_INST_HH__
-
-#include "arch/generic/pseudo_inst.hh"
-
-namespace ArmISA
-{
-
-using GenericISA::m5PageFault;
-
-} // namespace ArmISA
-
-#endif // __ARCH_ARM_PSEUDO_INST_HH__
-
Source('decode_cache.cc')
Source('decoder.cc')
Source('mmu.cc')
-Source('pseudo_inst.cc')
SimObject('BaseInterrupts.py')
SimObject('BaseISA.py')
+++ /dev/null
-/*
- * Copyright (c) 2014 Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "arch/generic/pseudo_inst.hh"
-
-#include "base/logging.hh"
-
-class ThreadContext;
-
-using namespace GenericISA;
-
-void
-GenericISA::m5PageFault(ThreadContext *tc)
-{
- panic("m5PageFault not implemented for current ISA");
-}
+++ /dev/null
-/*
- * Copyright (c) 2014 Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __ARCH_GENERIC_PSEUDO_INST_HH__
-#define __ARCH_GENERIC_PSEUDO_INST_HH__
-
-class ThreadContext;
-
-namespace GenericISA {
-
-/*
- * This function is executed when the simulation is executing the pagefault
- * handler in System Emulation mode.
- */
-void
-m5PageFault(ThreadContext *tc);
-
-} // namespace GenericISA
-
-#endif // __ARCH_GENERIC_PSEUDO_INST_HH__
-
+++ /dev/null
-/*
- * Copyright (c) 2014 Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __ARCH_MIPS_PSEUDO_INST_HH__
-#define __ARCH_MIPS_PSEUDO_INST_HH__
-
-#include "arch/generic/pseudo_inst.hh"
-
-namespace MipsISA
-{
-
-using GenericISA::m5PageFault;
-
-} // namespace MipsISA
-
-#endif // __ARCH_MIPS_PSEUDO_INST_HH__
-
+++ /dev/null
-/*
- * Copyright (c) 2014 Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __ARCH_POWER_PSEUDO_INST_HH__
-#define __ARCH_POWER_PSEUDO_INST_HH__
-
-#include "arch/generic/pseudo_inst.hh"
-
-namespace PowerISA
-{
-
-using GenericISA::m5PageFault;
-
-} // namespace PowerISA
-
-#endif // __ARCH_POWER_PSEUDO_INST_HH__
-
+++ /dev/null
-/*
- * Copyright (c) 2014 Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __ARCH_RISCV_PSEUDO_INST_HH__
-#define __ARCH_RISCV_PSEUDO_INST_HH__
-
-#include "arch/generic/pseudo_inst.hh"
-
-namespace RiscvISA
-{
-
-using GenericISA::m5PageFault;
-
-} // namespace RiscvISA
-
-#endif // __ARCH_RISCV_PSEUDO_INST_HH__
+++ /dev/null
-/*
- * Copyright (c) 2014 Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __ARCH_SPARC_PSEUDO_INST_HH__
-#define __ARCH_SPARC_PSEUDO_INST_HH__
-
-#include "arch/generic/pseudo_inst.hh"
-
-namespace SparcISA
-{
-
-using GenericISA::m5PageFault;
-
-} // namespace SparcISA
-
-#endif // __ARCH_SPARC_PSEUDO_INST_HH__
-
Source('pagetable.cc')
Source('pagetable_walker.cc')
Source('process.cc')
-Source('pseudo_inst.cc')
Source('remote_gdb.cc')
Source('tlb.cc')
Source('types.cc')
} // namespace IntelMP
-/* memory mappings for KVMCpu in SE mode */
-const Addr syscallCodeVirtAddr = 0xffff800000000000;
-const Addr GDTVirtAddr = 0xffff800000001000;
-const Addr IDTVirtAddr = 0xffff800000002000;
-const Addr TSSVirtAddr = 0xffff800000003000;
-const Addr TSSPhysAddr = 0x63000;
-const Addr ISTVirtAddr = 0xffff800000004000;
-const Addr PFHandlerVirtAddr = 0xffff800000005000;
-const Addr MMIORegionVirtAddr = 0xffffc90000000000;
-const Addr MMIORegionPhysAddr = 0xffff0000;
-
void installSegDesc(ThreadContext *tc, SegmentRegIndex seg,
SegDescriptor desc, bool longmode);
#include "arch/x86/linux/linux.hh"
#include "arch/x86/process.hh"
#include "arch/x86/registers.hh"
+#include "arch/x86/se_workload.hh"
#include "base/trace.hh"
#include "cpu/thread_context.hh"
#include "kern/linux/linux.hh"
}
}
+void
+EmuLinux::event(ThreadContext *tc)
+{
+ Process *process = tc->getProcessPtr();
+ auto pcState = tc->pcState();
+
+ if (process->kvmInSE) {
+ Addr pc_page = mbits(pcState.pc(), 63, 12);
+ if (pc_page == syscallCodeVirtAddr) {
+ syscall(tc);
+ return;
+ } else if (pc_page == PFHandlerVirtAddr) {
+ pageFault(tc);
+ return;
+ }
+ }
+ warn("Unexpected workload event at pc %#x.", pcState.pc());
+}
+
+void
+EmuLinux::pageFault(ThreadContext *tc)
+{
+ Process *p = tc->getProcessPtr();
+ if (!p->fixupFault(tc->readMiscReg(MISCREG_CR2))) {
+ PortProxy &proxy = tc->getVirtProxy();
+ // at this point we should have 6 values on the interrupt stack
+ int size = 6;
+ uint64_t is[size];
+ // reading the interrupt handler stack
+ proxy.readBlob(ISTVirtAddr + PageBytes - size * sizeof(uint64_t),
+ &is, sizeof(is));
+ panic("Page fault at addr %#x\n\tInterrupt handler stack:\n"
+ "\tss: %#x\n"
+ "\trsp: %#x\n"
+ "\trflags: %#x\n"
+ "\tcs: %#x\n"
+ "\trip: %#x\n"
+ "\terr_code: %#x\n",
+ tc->readMiscReg(MISCREG_CR2),
+ is[5], is[4], is[3], is[2], is[1], is[0]);
+ }
+}
+
} // namespace X86ISA
X86ISA::EmuLinux *
::Loader::Arch getArch() const override { return ::Loader::X86_64; }
void syscall(ThreadContext *tc) override;
+ void event(ThreadContext *tc) override;
+
+ void pageFault(ThreadContext *tc);
struct SyscallABI64 :
public GenericSyscallABI64, public X86Linux::SyscallABI
#include "arch/x86/isa_traits.hh"
#include "arch/x86/regs/misc.hh"
#include "arch/x86/regs/segment.hh"
+#include "arch/x86/se_workload.hh"
#include "arch/x86/types.hh"
#include "base/loader/elf_object.hh"
#include "base/loader/object_file.hh"
/** Page fault handler */
uint8_t faultBlob[] = {
- // mov %rax, (0xffffc90000005700)
- 0x48, 0xa3, 0x00, 0x61, 0x00,
+ // mov %rax, (0xffffc90000007000)
+ 0x48, 0xa3, 0x00, 0x70, 0x00,
0x00, 0x00, 0xc9, 0xff, 0xff,
// add $0x8, %rsp # skip error
0x48, 0x83, 0xc4, 0x08,
+++ /dev/null
-/*
- * Copyright (c) 2014 Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "arch/x86/pseudo_inst.hh"
-
-#include "arch/x86/fs_workload.hh"
-#include "arch/x86/isa_traits.hh"
-#include "cpu/thread_context.hh"
-#include "debug/PseudoInst.hh"
-#include "mem/se_translating_port_proxy.hh"
-#include "sim/process.hh"
-
-using namespace X86ISA;
-
-namespace X86ISA {
-
-/*
- * This function is executed when the simulation is executing the pagefault
- * handler in System Emulation mode.
- */
-void
-m5PageFault(ThreadContext *tc)
-{
- DPRINTF(PseudoInst, "PseudoInst::m5PageFault()\n");
-
- Process *p = tc->getProcessPtr();
- if (!p->fixupFault(tc->readMiscReg(MISCREG_CR2))) {
- PortProxy &proxy = tc->getVirtProxy();
- // at this point we should have 6 values on the interrupt stack
- int size = 6;
- uint64_t is[size];
- // reading the interrupt handler stack
- proxy.readBlob(ISTVirtAddr + PageBytes - size * sizeof(uint64_t),
- &is, sizeof(is));
- panic("Page fault at addr %#x\n\tInterrupt handler stack:\n"
- "\tss: %#x\n"
- "\trsp: %#x\n"
- "\trflags: %#x\n"
- "\tcs: %#x\n"
- "\trip: %#x\n"
- "\terr_code: %#x\n",
- tc->readMiscReg(MISCREG_CR2),
- is[5], is[4], is[3], is[2], is[1], is[0]);
- }
-}
-
-} // namespace X86ISA
+++ /dev/null
-/*
- * Copyright (c) 2014 Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __ARCH_X86_PSEUDO_INST_HH__
-#define __ARCH_X86_PSEUDO_INST_HH__
-
-class ThreadContext;
-
-namespace X86ISA
-{
-
-void m5PageFault(ThreadContext *tc);
-
-} // namespace X86ISA
-
-#endif // __ARCH_X86_PSEUDO_INST_HH__
--- /dev/null
+/*
+ * Copyright 2020 Google Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ARCH_X86_SE_WORKLOAD_HH__
+#define __ARCH_X86_SE_WORKLOAD_HH__
+
+#include "base/types.hh"
+
+namespace X86ISA
+{
+
+/* memory mappings for KVMCpu in SE mode */
+const Addr syscallCodeVirtAddr = 0xffff800000000000;
+const Addr GDTVirtAddr = 0xffff800000001000;
+const Addr IDTVirtAddr = 0xffff800000002000;
+const Addr TSSVirtAddr = 0xffff800000003000;
+const Addr TSSPhysAddr = 0x63000;
+const Addr ISTVirtAddr = 0xffff800000004000;
+const Addr PFHandlerVirtAddr = 0xffff800000005000;
+const Addr MMIORegionVirtAddr = 0xffffc90000000000;
+const Addr MMIORegionPhysAddr = 0xffff0000;
+
+} // namespace X86ISA
+
+#endif // __ARCH_X86_SE_WORKLOAD_HH__
class ThreadContext;
-#include "arch/pseudo_inst.hh"
#include "arch/utility.hh"
#include "base/bitfield.hh"
#include "base/types.hh" // For Tick and Addr data types.
warn("Unimplemented m5 op (%#x)\n", func);
return false;
- /* SE mode functions */
- case M5OP_SE_PAGE_FAULT:
- invokeSimcall<ABI>(tc, TheISA::m5PageFault);
- return true;
-
/* dist-gem5 functions */
case M5OP_DIST_TOGGLE_SYNC:
invokeSimcall<ABI>(tc, togglesync);
projects / gem5.git / commitdiff