# Explain what the requested budget will be used for?
+To improve the speed of the GUI front-end, to make it possible to
+handle larger ASIC designs, to add LVS capability, improve the internal
+data format (to better handle mixed case module and signal names), integrate
+the Static Timing Analysis tool (HITAS, TAGLE), to complete the conversion
+to python 3,
+to try smaller geometry ASICs (beginning with 130nm), and potentially
+investigate using multi-processing to speed up completion.
# Does the project have other funding sources, both past and present?
LIP6 is part of Sorbonne University. The developers and maintainers
of Coriolis2, HITAS/TAGLE, and Alliance, are all employed by Sorbonne
-University.
+University. For the Libre-SOC 180nm ASIC development an NLnet Grant
+was received, most of this work is now completed.
# Compare your own project with existing or historical efforts.
## What are significant technical challenges you expect to solve during the project, if any?
+The size of databases for VLSI ASIC Layout are extremely large, and a huge
+amount of computing power is needed, in one single machine. In addition
+a huge amount of specialist knowledge of VLSI and silicon is needed,
+completely separately from actual Software Engineering skills. These
+three factors combine to really tax the development of VLSI tools.
## Describe the ecosystem of the project, and how you will engage with relevant actors and promote the outcomes?
-
+The entire source code is developed and available immediately, through LIP6
+online resources including gitlab instance, mailing list, and website.
+Sorbonne University and LIP6 both have twitter accounts, and the developers
+write Academic papers and present at conferences. In addition, they work
+with the Libre-SOC Team to promote milestones and developments.
# Extra info to be submitted