return IS_ALU(bundle->tag);
}
-/* Registers/SSA are distinguish in the backend by the bottom-most bit */
-
-#define IS_REG (1)
-
static inline unsigned
make_compiler_temp(compiler_context *ctx)
{
static inline unsigned
make_compiler_temp_reg(compiler_context *ctx)
{
- return ((ctx->func->impl->reg_alloc + ctx->temp_alloc++) << 1) | IS_REG;
+ return ((ctx->func->impl->reg_alloc + ctx->temp_alloc++) << 1) | PAN_IS_REG;
}
static inline unsigned
return nir_ssa_index(src->ssa);
else {
assert(!src->reg.indirect);
- return (src->reg.reg->index << 1) | IS_REG;
+ return (src->reg.reg->index << 1) | PAN_IS_REG;
}
}
return (dst->ssa.index << 1) | 0;
else {
assert(!dst->reg.indirect);
- return (dst->reg.reg->index << 1) | IS_REG;
+ return (dst->reg.reg->index << 1) | PAN_IS_REG;
}
}
/* TODO: Registers? */
unsigned src = ins->src[1];
- if (src & IS_REG) continue;
+ if (src & PAN_IS_REG) continue;
/* There might be a source modifier, too */
if (mir_nontrivial_source2_mod(ins)) continue;
unsigned from = ins->src[1];
unsigned to = ins->dest;
- if (!(to & IS_REG)) continue;
- if (from & IS_REG) continue;
+ if (!(to & PAN_IS_REG)) continue;
+ if (from & PAN_IS_REG) continue;
if (ins->has_inline_constant) continue;
if (ins->has_constants) continue;
if (to >= SSA_FIXED_MINIMUM) continue;
if (from >= SSA_FIXED_MINIMUM) continue;
- if (to & IS_REG) continue;
- if (from & IS_REG) continue;
+ if (to & PAN_IS_REG) continue;
+ if (from & PAN_IS_REG) continue;
/* Constant propagation is not handled here, either */
if (ins->has_inline_constant) continue;
if (ins->alu.op != midgard_alu_op_imov) continue;
if (!ins->invert) continue;
if (mir_nontrivial_source2_mod_simple(ins)) continue;
- if (ins->src[1] & IS_REG) continue;
+ if (ins->src[1] & PAN_IS_REG) continue;
/* Is it beneficial to propagate? */
if (!mir_single_use(ctx, ins->src[1])) continue;
static bool
is_ssa_or_constant(unsigned node)
{
- return !(node & IS_REG) || (node == SSA_FIXED_REGISTER(26));
+ return !(node & PAN_IS_REG) || (node == SSA_FIXED_REGISTER(26));
}
bool
if (ins->type != TAG_ALU_4) continue;
if (!OP_IS_INTEGER_CMP(ins->alu.op)) continue;
- if ((ins->src[0] & IS_REG) || (ins->src[1] & IS_REG)) continue;
+ if ((ins->src[0] & PAN_IS_REG) || (ins->src[1] & PAN_IS_REG)) continue;
if (!mir_single_use(ctx, ins->src[0]) || !mir_single_use(ctx, ins->src[1])) continue;
bool a_inverted = mir_is_inverted(ctx, ins->src[0]);
if (ins->type != TAG_ALU_4) continue;
if (!midgard_is_branch_unit(ins->unit)) continue;
if (!ins->branch.conditional) continue;
- if (ins->src[0] & IS_REG) continue;
+ if (ins->src[0] & PAN_IS_REG) continue;
if (mir_strip_inverted(ctx, ins->src[0])) {
ins->branch.invert_conditional = !ins->branch.invert_conditional;
unsigned frcp = ins->src[1];
unsigned to = ins->dest;
- if (frcp & IS_REG) continue;
- if (to & IS_REG) continue;
+ if (frcp & PAN_IS_REG) continue;
+ if (to & PAN_IS_REG) continue;
bool frcp_found = false;
unsigned frcp_component = 0;
unsigned vary = ins->src[0];
unsigned to = ins->dest;
- if (vary & IS_REG) continue;
- if (to & IS_REG) continue;
+ if (vary & PAN_IS_REG) continue;
+ if (to & PAN_IS_REG) continue;
if (!mir_single_use(ctx, vary)) continue;
/* Check for a varying source. If we find it, we rewrite */
/* We do need the move for safety for a non-SSA dest, or if
* we're being fed into a special class */
- bool needs_move = ins->dest & IS_REG;
+ bool needs_move = ins->dest & PAN_IS_REG;
needs_move |= mir_special_index(ctx, ins->dest);
if (needs_move) {