litedram: Fix DRAM init mem using too many address bits

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

diff --git a/litedram/gen-src/dram-init-mem.vhdl b/litedram/gen-src/dram-init-mem.vhdl
index 13bd0ce141dcfed6f0c9f81ca51f22ab42dae597..a1b87d38846d779e5ad6cc6956837131380060fb 100644 (file)
--- a/litedram/gen-src/dram-init-mem.vhdl
+++ b/litedram/gen-src/dram-init-mem.vhdl
@@ -24,7 +24,7 @@ architecture rtl of dram_init_mem is
     constant INIT_RAM_SIZE    : integer := 16384;
     constant RND_PAYLOAD_SIZE : integer := round_up(EXTRA_PAYLOAD_SIZE, 8);
     constant TOTAL_RAM_SIZE   : integer := INIT_RAM_SIZE + RND_PAYLOAD_SIZE;
-    constant INIT_RAM_ABITS   : integer := log2ceil(TOTAL_RAM_SIZE);
+    constant INIT_RAM_ABITS   : integer := log2ceil(TOTAL_RAM_SIZE-1);
     constant INIT_RAM_FILE    : string := "litedram_core.init";
 
     type ram_t is array(0 to (TOTAL_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0);

diff --git a/litedram/generated/arty/litedram-initmem.vhdl b/litedram/generated/arty/litedram-initmem.vhdl
index 13bd0ce141dcfed6f0c9f81ca51f22ab42dae597..a1b87d38846d779e5ad6cc6956837131380060fb 100644 (file)
--- a/litedram/generated/arty/litedram-initmem.vhdl
+++ b/litedram/generated/arty/litedram-initmem.vhdl
@@ -24,7 +24,7 @@ architecture rtl of dram_init_mem is
     constant INIT_RAM_SIZE    : integer := 16384;
     constant RND_PAYLOAD_SIZE : integer := round_up(EXTRA_PAYLOAD_SIZE, 8);
     constant TOTAL_RAM_SIZE   : integer := INIT_RAM_SIZE + RND_PAYLOAD_SIZE;
-    constant INIT_RAM_ABITS   : integer := log2ceil(TOTAL_RAM_SIZE);
+    constant INIT_RAM_ABITS   : integer := log2ceil(TOTAL_RAM_SIZE-1);
     constant INIT_RAM_FILE    : string := "litedram_core.init";
 
     type ram_t is array(0 to (TOTAL_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0);

diff --git a/litedram/generated/nexys-video/litedram-initmem.vhdl b/litedram/generated/nexys-video/litedram-initmem.vhdl
index 13bd0ce141dcfed6f0c9f81ca51f22ab42dae597..a1b87d38846d779e5ad6cc6956837131380060fb 100644 (file)
--- a/litedram/generated/nexys-video/litedram-initmem.vhdl
+++ b/litedram/generated/nexys-video/litedram-initmem.vhdl
@@ -24,7 +24,7 @@ architecture rtl of dram_init_mem is
     constant INIT_RAM_SIZE    : integer := 16384;
     constant RND_PAYLOAD_SIZE : integer := round_up(EXTRA_PAYLOAD_SIZE, 8);
     constant TOTAL_RAM_SIZE   : integer := INIT_RAM_SIZE + RND_PAYLOAD_SIZE;
-    constant INIT_RAM_ABITS   : integer := log2ceil(TOTAL_RAM_SIZE);
+    constant INIT_RAM_ABITS   : integer := log2ceil(TOTAL_RAM_SIZE-1);
     constant INIT_RAM_FILE    : string := "litedram_core.init";
 
     type ram_t is array(0 to (TOTAL_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0);

diff --git a/litedram/generated/sim/litedram-initmem.vhdl b/litedram/generated/sim/litedram-initmem.vhdl
index 7abaf48068ace8aaf313901da49a9ef79c4602f8..b6886f99ba9d9b2bf89512202b467b57c612f33e 100644 (file)
--- a/litedram/generated/sim/litedram-initmem.vhdl
+++ b/litedram/generated/sim/litedram-initmem.vhdl
@@ -24,7 +24,7 @@ architecture rtl of dram_init_mem is
     constant INIT_RAM_SIZE    : integer := 16384;
     constant RND_PAYLOAD_SIZE : integer := round_up(EXTRA_PAYLOAD_SIZE, 8);
     constant TOTAL_RAM_SIZE   : integer := INIT_RAM_SIZE + RND_PAYLOAD_SIZE;
-    constant INIT_RAM_ABITS   : integer := log2ceil(TOTAL_RAM_SIZE);
+    constant INIT_RAM_ABITS   : integer := log2ceil(TOTAL_RAM_SIZE-1);
     constant INIT_RAM_FILE    : string := "litedram/generated/sim/litedram_core.init";
 
     type ram_t is array(0 to (TOTAL_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0);