Fix some of the memory leaks related to writebacks

src/cpu/memtest/memtest.cc:
    Add the [] to a delete to make it work correctly
src/mem/cache/cache_impl.hh:
    Fix one of the memory leaks

--HG--
extra : convert_revision : 64c7465c68a084efe38a62419205518b24d852a7

diff --git a/src/cpu/memtest/memtest.cc b/src/cpu/memtest/memtest.cc
index 8b3e9a11e42f3f1fcab690ce25a5438371ecd386..607cf10662623ddc429a1bb5b4bb1a7cf91e473b 100644 (file)
--- a/src/cpu/memtest/memtest.cc
+++ b/src/cpu/memtest/memtest.cc
@@ -369,7 +369,7 @@ MemTest::tick()
         //This means we assume CPU does write forwarding to reads that alias something
         //in the cpu store buffer.
         if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) {
-            delete result;
+            delete [] result;
             delete req;
             return;
         }

diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 056f6033f84f2127f25cc79a43e0db5d6ebae83f..d8aab0e58e6f702d3f0123cbf7b349a03fafb87c 100644 (file)
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -570,8 +570,10 @@ Cache<TagStore,Coherence>::access(PacketPtr &pkt)
         }
     }
     while (!writebacks.empty()) {
-        missQueue->doWriteback(writebacks.front());
+        PacketPtr wbPkt = writebacks.front();
+        missQueue->doWriteback(wbPkt);
         writebacks.pop_front();
+        delete wbPkt;
     }
 
     DPRINTF(Cache, "%s %x %s\n", pkt->cmdString(), pkt->getAddr(),
@@ -721,8 +723,10 @@ Cache<TagStore,Coherence>::handleResponse(PacketPtr &pkt)
             blk = handleFill(blk, (MSHR*)pkt->senderState,
                                    new_state, writebacks, pkt);
             while (!writebacks.empty()) {
-                    missQueue->doWriteback(writebacks.front());
-                    writebacks.pop_front();
+                PacketPtr wbPkt = writebacks.front();
+                missQueue->doWriteback(wbPkt);
+                writebacks.pop_front();
+                delete wbPkt;
             }
         }
         missQueue->handleResponse(pkt, curTick + hitLatency);
@@ -1040,8 +1044,10 @@ return 0;
             // There was a cache hit.
             // Handle writebacks if needed
             while (!writebacks.empty()){
-                memSidePort->sendAtomic(writebacks.front());
+                PacketPtr wbPkt = writebacks.front();
+                memSidePort->sendAtomic(wbPkt);
                 writebacks.pop_front();
+                delete wbPkt;
             }
 
             hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;