hyperlink to SVP64-Single

diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index c17a2022b2327c7e78836436e7d844a35ccc7269..00e8fdc9a5916fdf16620994b44b9fb2935ac334 100644 (file)
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -312,7 +312,8 @@ Scheme.
 * **0000** - all 24 bits bits 8-31 are zero (0x000000)
 * **!zero** - bits 8-31 may be any value *other* than zero (0x000001-0xffffff)
 * **nnnn** - bits 8-31 may be any value in the range 0x000000 to 0xffffff
-* **SVP64Single** - a (TBD) Encoding that is near-identical to SVP64
+* **SVP64Single** - a ([TBD](https://bugs.libre-soc.org/show_bug.cgi?id=905))
+  Encoding that is near-identical to SVP64
   except that it is not a Vector Operation (equivalent to hard-coded VL=1
   at all times). Predication is permitted, Element-width-overrides is
   permitted, Saturation is permitted. SVP64Single is a **scalar** augmentation