ac/gpu_info: add kernel_flushes_tc_l2_after_ib

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 1c7abdb87cb64d05dc55513640f7c4b1762ebedc..4eeb6042eef6ddcbbfbfc4c6f19d9c090d80fbd6 100644 (file)
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -324,6 +324,9 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
        info->has_gpu_reset_counter_query = false;
        info->has_eqaa_surface_allocator = true;
        info->has_format_bc1_through_bc7 = true;
+       /* DRM 3.1.0 doesn't flush TC for VI correctly. */
+       info->kernel_flushes_tc_l2_after_ib = info->chip_class != VI ||
+                                             info->drm_minor >= 2;
 
        info->num_render_backends = amdinfo->rb_pipes;
        /* The value returned by the kernel driver was wrong. */
@@ -479,6 +482,7 @@ void ac_print_gpu_info(struct radeon_info *info)
        printf("    has_gpu_reset_counter_query = %u\n", info->has_gpu_reset_counter_query);
        printf("    has_eqaa_surface_allocator = %u\n", info->has_eqaa_surface_allocator);
        printf("    has_format_bc1_through_bc7 = %u\n", info->has_format_bc1_through_bc7);
+       printf("    kernel_flushes_tc_l2_after_ib = %u\n", info->kernel_flushes_tc_l2_after_ib);
 
        printf("Shader core info:\n");
        printf("    max_shader_clock = %i\n", info->max_shader_clock);

diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index 9c4c6cb11f0f1ea5c672c1d408c77856be9f0974..5e404714db6056090eedb3d9c409b3d49f404c6c 100644 (file)
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -104,6 +104,7 @@ struct radeon_info {
        bool                        has_gpu_reset_counter_query;
        bool                        has_eqaa_surface_allocator;
        bool                        has_format_bc1_through_bc7;
+       bool                        kernel_flushes_tc_l2_after_ib;
 
        /* Shader cores. */
        uint32_t                    r600_max_quad_pipes; /* wave size / 16 */

diff --git a/src/gallium/drivers/radeonsi/si_gfx_cs.c b/src/gallium/drivers/radeonsi/si_gfx_cs.c
index 0af16dd3474f57062e214abf2409c27c592a0f6b..ec74c1bc70368363cdf87a85a0b696ce0277f527 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_gfx_cs.c
+++ b/src/gallium/drivers/radeonsi/si_gfx_cs.c
@@ -74,8 +74,7 @@ void si_flush_gfx_cs(struct si_context *ctx, unsigned flags,
        if (ctx->gfx_flush_in_progress)
                return;
 
-       if (ctx->chip_class == VI && ctx->screen->info.drm_minor <= 1) {
-               /* DRM 3.1.0 doesn't flush TC for VI correctly. */
+       if (!ctx->screen->info.kernel_flushes_tc_l2_after_ib) {
                wait_flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
                              SI_CONTEXT_CS_PARTIAL_FLUSH |
                              SI_CONTEXT_INV_GLOBAL_L2;

diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index 108c1af99851504f40ccf0bedcb29712737d7008..1b029e94969610a6bb09e787b3026bec4a58ede7 100644 (file)
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -538,6 +538,7 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
     ws->info.has_gpu_reset_counter_query = ws->info.drm_minor >= 43;
     ws->info.has_eqaa_surface_allocator = false;
     ws->info.has_format_bc1_through_bc7 = ws->info.drm_minor >= 31;
+    ws->info.kernel_flushes_tc_l2_after_ib = true;
 
     ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL;