swr/rast: WIP builder rewrite.

Start removing avx2 macros for functionality that exists in llvm.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

diff --git a/src/gallium/drivers/swr/rasterizer/codegen/gen_llvm_ir_macros.py b/src/gallium/drivers/swr/rasterizer/codegen/gen_llvm_ir_macros.py
index 113c616f6ae87899602809c6780761179aca19ef..3e1fbfe88e66a582696c3352aa5ac1049ada7cf2 100644 (file)
--- a/src/gallium/drivers/swr/rasterizer/codegen/gen_llvm_ir_macros.py
+++ b/src/gallium/drivers/swr/rasterizer/codegen/gen_llvm_ir_macros.py
@@ -53,12 +53,7 @@ intrinsics = [
         ['VMINPS', 'x86_avx_min_ps_256', ['a', 'b']],
         ['VMAXPS', 'x86_avx_max_ps_256', ['a', 'b']],
         ['VROUND', 'x86_avx_round_ps_256', ['a', 'rounding']],
-        ['VCMPPS', 'x86_avx_cmp_ps_256', ['a', 'b', 'cmpop']],
-        ['VBLENDVPS', 'x86_avx_blendv_ps_256', ['a', 'b', 'mask']],
         ['BEXTR_32', 'x86_bmi_bextr_32', ['src', 'control']],
-        ['VMASKLOADD', 'x86_avx2_maskload_d_256', ['src', 'mask']],
-        ['VMASKMOVPS', 'x86_avx_maskload_ps_256', ['src', 'mask']],
-        ['VMASKSTOREPS', 'x86_avx_maskstore_ps_256', ['src', 'mask', 'val']],
         ['VPSHUFB', 'x86_avx2_pshuf_b', ['a', 'b']],
         ['VPERMD', 'x86_avx2_permd', ['a', 'idx']],
         ['VPERMPS', 'x86_avx2_permps', ['idx', 'a']],

diff --git a/src/gallium/drivers/swr/rasterizer/jitter/builder_misc.h b/src/gallium/drivers/swr/rasterizer/jitter/builder_misc.h
index 9660bc65f02d783e79731eb9b562a31c0327b1a9..549f328ff4f8b539044b53030a80aade9acc3f1f 100644 (file)
--- a/src/gallium/drivers/swr/rasterizer/jitter/builder_misc.h
+++ b/src/gallium/drivers/swr/rasterizer/jitter/builder_misc.h
@@ -96,15 +96,6 @@ CallInst *CALL(Value *Callee, Value* arg);
 CallInst *CALL2(Value *Callee, Value* arg1, Value* arg2);
 CallInst *CALL3(Value *Callee, Value* arg1, Value* arg2, Value* arg3);
 
-Value *VCMPPS_EQ(Value* a, Value* b)    { return VCMPPS(a, b, C((uint8_t)_CMP_EQ_OQ)); }
-Value *VCMPPS_LT(Value* a, Value* b)    { return VCMPPS(a, b, C((uint8_t)_CMP_LT_OQ)); }
-Value *VCMPPS_LE(Value* a, Value* b)    { return VCMPPS(a, b, C((uint8_t)_CMP_LE_OQ)); }
-Value *VCMPPS_ISNAN(Value* a, Value* b) { return VCMPPS(a, b, C((uint8_t)_CMP_UNORD_Q)); }
-Value *VCMPPS_NEQ(Value* a, Value* b)   { return VCMPPS(a, b, C((uint8_t)_CMP_NEQ_OQ)); }
-Value *VCMPPS_GE(Value* a, Value* b)    { return VCMPPS(a, b, C((uint8_t)_CMP_GE_OQ)); }
-Value *VCMPPS_GT(Value* a, Value* b)    { return VCMPPS(a, b, C((uint8_t)_CMP_GT_OQ)); }
-Value *VCMPPS_NOTNAN(Value* a, Value* b){ return VCMPPS(a, b, C((uint8_t)_CMP_ORD_Q)); }
-
 Value *MASK(Value *vmask);
 Value *MASK_16(Value *vmask);