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raw | patch | inline | side by side (parent: 8740dd6)
sv.adde not sv.addeo
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 29 Sep 2022 18:00:30 +0000 (19:00 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 29 Sep 2022 18:00:30 +0000 (19:00 +0100)
src/openpower/decoder/isa/test_caller_svp64_bigint.py patch | blob | history

diff --git a/src/openpower/decoder/isa/test_caller_svp64_bigint.py b/src/openpower/decoder/isa/test_caller_svp64_bigint.py
index fc1f420c28260a01c018c81990cb8cf3b6f219b0..d14bf8e15636fc4d696e8f14eb008fe6c3ccd988 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svp64_bigint.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_bigint.py
@@ -34,7 +34,7 @@ class DecoderTestCase(FHDLTestCase):
         r5/r4: 0x8000_0000_0000_0000 0x0000_0000_0000_0001 =
         r1/r0: 0x8000_0000_0000_0002 0x0000_0000_0000_0000
         """
-        isa = SVP64Asm(['sv.addeo *0, *2, *4'
+        isa = SVP64Asm(['sv.adde *0, *2, *4'
                        ])
         lst = list(isa)
         print ("listing", lst)