update sv test comments

diff --git a/isa/rv64ui/sv_addi.S b/isa/rv64ui/sv_addi.S
index e86a3f36c6a91f64ba1a38a3121c4d25e77a89fd..123052cf02e1e9e42764f9cef9881783b660d028 100644 (file)
--- a/isa/rv64ui/sv_addi.S
+++ b/isa/rv64ui/sv_addi.S
@@ -4,7 +4,9 @@
 RVTEST_RV64U        # Define TVM used by program.
 
 
-# SV test: sets up x3 and x4 with data, sets VL to 2, and carries out
+# SV test: vector-vector add
+#
+# sets up x3 and x4 with data, sets VL to 2, and carries out
 # an "add 1 to x3".  which actually means "add 1 to x3 *AND* add 1 to x4"
 
 # Test code region.

diff --git a/isa/rv64ui/sv_addi_redirect.S b/isa/rv64ui/sv_addi_redirect.S
index 980cb5b4c483f924c6adda9e0397da471f2ccbef..61e92842147e295fc91295caa98997e06a3d9cb3 100644 (file)
--- a/isa/rv64ui/sv_addi_redirect.S
+++ b/isa/rv64ui/sv_addi_redirect.S
@@ -3,7 +3,9 @@
 
 RVTEST_RV64U        # Define TVM used by program.
 
-# SV test: sets up x3 and x4 with data, then sets up SV redirection
+# SV test: vector-vector (redirected) add
+#
+# sets up x3 and x4 with data, then sets up SV redirection
 # from register x16 to register x3 with a VL of 2.  the add is carried out
 # on x16 and the redirection means "actually, we want to do that add on x3"
 # and the VL means "actually we want to do that add on x3 *AND* x4"

diff --git a/isa/rv64ui/sv_addi_scalar_src.S b/isa/rv64ui/sv_addi_scalar_src.S
index 2d1e974acdcfd16d8def35142362a954fe983a10..fda4e0c551aecdb90580060bdd406f3d1c661489 100644 (file)
--- a/isa/rv64ui/sv_addi_scalar_src.S
+++ b/isa/rv64ui/sv_addi_scalar_src.S
@@ -4,7 +4,9 @@
 RVTEST_RV64U        # Define TVM used by program.
 
 
-# SV test: sets up x6 data as a scalar, sets VL to 2, and carries out
+# SV test: scalar-to-vector add
+#
+# sets up x6 data as a scalar, sets VL to 2, and carries out
 # an "add 1 to x6 and store in x3".
 # which actually means:
 # "add add 1 to x6 and store in x3" *AND*