Bugfix in opt_expr handling of a<0 and a>=0

Signed-off-by: Clifford Wolf <clifford@clifford.at>

diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index 0ba233c6207027c84a4ed08749771e64146dcd6d..610edc5e992436996ec5cdaf46f40c8508f5dfd4 100644 (file)
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -1406,7 +1406,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
                        if (sigConst.is_fully_const() && sigConst.is_fully_def() && var_signed == false)
                        {
                                if (sigConst.is_fully_zero()) {
-                                       RTLIL::SigSpec a_prime(RTLIL::State::S0, 1);
+                                       RTLIL::SigSpec a_prime(RTLIL::State::S0, GetSize(cell->getPort("\\Y")));
                                        if (is_lt) {
                                                log("Replacing %s cell `%s' (implementing unsigned X<0) with constant false.\n",
                                                                log_id(cell->type), log_id(cell));