[simplify-rtx] PR 65235: Calculate element size correctly when simplifying (vec_selec...

	PR rtl-optimization 65235
	* simplify-rtx.c (simplify_binary_operation_1, VEC_SELECT case):
	When first element of vec_concat is const_int, calculate its size
	using second element.

	PR rtl-optimization 65235
	* gcc.target/aarch64/pr65235_1.c: New test.

From-SVN: r221387

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 35c6a95c51cb1e0feb189b8ecd399b8bba2afdb9..3fb408a605f28acb4a11e81144a94b8c51bf1256 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2015-03-12  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+       PR rtl-optimization 65235
+       * simplify-rtx.c (simplify_binary_operation_1, VEC_SELECT case):
+       When first element of vec_concat is const_int, calculate its size
+       using second element.
+
 2015-03-12  Richard Biener  <rguenther@suse.de>
 
        PR middle-end/65270

diff --git a/gcc/simplify-rtx.c b/gcc/simplify-rtx.c
index a003b4179aa692700237448367955e13da3766e6..5d1749829bdc883a1d61ae7a72c5e028d70918c2 100644 (file)
--- a/gcc/simplify-rtx.c
+++ b/gcc/simplify-rtx.c
@@ -3555,7 +3555,21 @@ simplify_binary_operation_1 (enum rtx_code code, machine_mode mode,
          while (GET_MODE (vec) != mode
                 && GET_CODE (vec) == VEC_CONCAT)
            {
-             HOST_WIDE_INT vec_size = GET_MODE_SIZE (GET_MODE (XEXP (vec, 0)));
+             HOST_WIDE_INT vec_size;
+
+             if (CONST_INT_P (XEXP (vec, 0)))
+               {
+                 /* vec_concat of two const_ints doesn't make sense with
+                    respect to modes.  */
+                 if (CONST_INT_P (XEXP (vec, 1)))
+                   return 0;
+
+                 vec_size = GET_MODE_SIZE (GET_MODE (trueop0))
+                            - GET_MODE_SIZE (GET_MODE (XEXP (vec, 1)));
+               }
+             else
+               vec_size = GET_MODE_SIZE (GET_MODE (XEXP (vec, 0)));
+
              if (offset < vec_size)
                vec = XEXP (vec, 0);
              else

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index baf5f426f5cbc77cd07fd13a8f4ba4eababc03d9..24318b388b7369f976f4fb29bf0b6c81b22ff55c 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2015-03-12  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+       PR rtl-optimization 65235
+       * gcc.target/aarch64/pr65235_1.c: New test.
+
 2015-03-12  Dominik Vogt  <vogt@linux.vnet.ibm.com>
 
        * gcc.target/s390/hotpatch-21.c: New test for hotpatch alignment.

diff --git a/gcc/testsuite/gcc.target/aarch64/pr65235_1.c b/gcc/testsuite/gcc.target/aarch64/pr65235_1.c
new file mode 100644 (file)
index 0000000..ca12cd5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/pr65235_1.c
@@ -0,0 +1,30 @@
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+#include "arm_neon.h"
+
+int
+main (int argc, char** argv)
+{
+  int64x1_t val1;
+  int64x1_t val2;
+  int64x1_t val3;
+  uint64x1_t val13;
+  uint64x2_t val14;
+  uint64_t got;
+  uint64_t exp;
+  val1 = vcreate_s64(UINT64_C(0xffffffff80008000));
+  val2 = vcreate_s64(UINT64_C(0x0000f38d00000000));
+  val3 = vcreate_s64(UINT64_C(0xffff7fff0000809b));
+  /* Expect: "val13" = 8000000000001553.  */
+  val13 = vcreate_u64 (UINT64_C(0x8000000000001553));
+  /* Expect: "val14" = 0010 0000 0000 0002 0000 0000 0000 0000.  */
+  val14 = vcombine_u64(vcgt_s64(vqrshl_s64(val1, val2),
+                               vshr_n_s64(val3, 18)),
+                      vshr_n_u64(val13, 11));
+  /* Should be 0000000000000000.  */
+  got = vgetq_lane_u64(val14, 0);
+  exp = 0;
+  if(exp != got)
+    __builtin_abort ();
+}