Added in endianness conversion on memory accesses as the data goes out. This will...

--HG--
extra : convert_revision : b8191cab09ab8f3ced05693293f058382319ed8e

diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index 4facea9f9527c0300bc08cc2e9defbf702209eee..37972416619bd584cc0ff6937e1b4323750f4607 100644 (file)
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -596,7 +596,11 @@ LSQUnit<Impl>::writebackStores()
 
         assert(!inst->memData);
         inst->memData = new uint8_t[64];
-        memcpy(inst->memData, (uint8_t *)&storeQueue[storeWBIdx].data,
+
+        TheISA::IntReg convertedData =
+            TheISA::htog(storeQueue[storeWBIdx].data);
+
+        memcpy(inst->memData, (uint8_t *)&convertedData,
                req->getSize());
 
         PacketPtr data_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast);