converted test_caller_svp64_matrix.py to new reg format

https://bugs.libre-soc.org/show_bug.cgi?id=884#c0

diff --git a/src/openpower/decoder/isa/test_caller_svp64_matrix.py b/src/openpower/decoder/isa/test_caller_svp64_matrix.py
index 130f94720ec42bc1cef1fa478fe7571f0c95d7e6..43f14c8e807d37b6c27a822002b5f02cb2b33662 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svp64_matrix.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_matrix.py
@@ -28,13 +28,13 @@ class DecoderTestCase(FHDLTestCase):
     def test_sv_remap1(self):
         """>>> lst = ["svshape 2, 2, 3, 0, 0",
                         "svremap 31, 1, 2, 3, 0, 0, 0",
-                       "sv.fmadds 0.v, 8.v, 16.v, 0.v"
+                       "sv.fmadds *0, *8, *16, *0"
                         ]
                 REMAP fmadds FRT, FRA, FRC, FRB
         """
         lst = SVP64Asm(["svshape 2, 2, 3, 0, 0",
                         "svremap 31, 1, 2, 3, 0, 0, 0",
-                       "sv.fmadds 0.v, 16.v, 32.v, 0.v"
+                       "sv.fmadds *0, *16, *32, *0"
                         ])
         lst = list(lst)
 
@@ -94,13 +94,13 @@ class DecoderTestCase(FHDLTestCase):
     def test_sv_remap2(self):
         """>>> lst = ["svshape 5, 4, 3, 0, 0",
                         "svremap 31, 1, 2, 3, 0, 0, 0",
-                       "sv.fmadds 0.v, 8.v, 16.v, 0.v"
+                       "sv.fmadds *0, *8, *16, *0"
                         ]
                 REMAP fmadds FRT, FRA, FRC, FRB
         """
         lst = SVP64Asm(["svshape 4, 3, 3, 0, 0",
                         "svremap 31, 1, 2, 3, 0, 0, 0",
-                       "sv.fmadds 0.v, 16.v, 32.v, 0.v"
+                       "sv.fmadds *0, *16, *32, *0"
                         ])
         lst = list(lst)