Clifford Wolf. The Yosys Open SYnthesis Suite. \\
\url{http://www.clifford.at/yosys/}
-\bibitem{bigsim}
-yosys-bigsim, a collection of real-world Verilog designs for regression testing purposes. \\
-\url{https://github.com/cliffordwolf/yosys-bigsim}
+%\bibitem{bigsim}
+%yosys-bigsim, a collection of real-world Verilog designs for regression testing purposes. \\
+%\url{https://github.com/cliffordwolf/yosys-bigsim}
-\bibitem{navre}
-Sebastien Bourdeauducq. Navré AVR clone (8-bit RISC). \\
-\url{http://opencores.org/project,navre}
+%\bibitem{navre}
+%Sebastien Bourdeauducq. Navré AVR clone (8-bit RISC). \\
+%\url{http://opencores.org/project,navre}
-\bibitem{amber}
-Conor Santifort. Amber ARM-compatible core. \\
-\url{http://opencores.org/project,amber}
+%\bibitem{amber}
+%Conor Santifort. Amber ARM-compatible core. \\
+%\url{http://opencores.org/project,amber}
-\bibitem{ABC}
-Berkeley Logic Synthesis and Verification Group. ABC: A System for Sequential Synthesis and Verification. \\
-\url{http://www.eecs.berkeley.edu/~alanmi/abc/}
+%\bibitem{ABC}
+%Berkeley Logic Synthesis and Verification Group. ABC: A System for Sequential Synthesis and Verification. \\
+%\url{http://www.eecs.berkeley.edu/~alanmi/abc/}
\bibitem{boolector}
Robert Brummayer and Armin Biere, Boolector: An Efficient SMT Solver for Bit-Vectors and Arrays\\