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diff --git a/openpower/sv/rfc/ls012.mdwn b/openpower/sv/rfc/ls012.mdwn
index 1ee99d5421ce4788177ce305e7bcca99009c4af3..21266a75a4da980bddcb41a9487e7e4d9db3cb42 100644 (file)
--- a/openpower/sv/rfc/ls012.mdwn
+++ b/openpower/sv/rfc/ls012.mdwn
@@ -14,6 +14,21 @@ of a borderline Vectoriseable Defined Word is `mv.swizzle` which
 only really becomes high-priority for Vector GPU and HPC Workloads,
 but has less merit as a Scalar-only operation.
 
+Power ISA Scalar (SFFS) has not been significantly advanced in 12 years.
+With VSX bring 914 instructions and 128-bit it is far too much for any
+new team to consider (10 years development effort) and far outside of
+Embedded or Tablet/Desktop/Laptop power budgets. Thus bringing Power Scalar
+up-to-date to modern standards is a reasonable goal, and the advantage is
+that lessons can be learned from other ISAs.
+
+SVP64 Prefixing - also known by the terms "Zero-Overhead-Loop-Prefixing"
+as well as "True-Scalable Vector Prefixing" - also literally brings new
+dimensions to the Power ISA. Thus when adding new Scalar "Defined Words"
+it has to unavoidably be taken into consideration their value when
+Vectorised.
+
+
+
 Instruction count guide and approximate priority order:
 
 * 6 - SVP64 Management [[ls008]] [[ls009]] [[ls010]]