\node[process] (astfe) [below of=ast, node distance=5em] {AST Frontend};
\node[data] (rtlil) [below of=astfe, node distance=5em, xshift=7.5em] {RTLIL};
\node[process] (pass) [right of=rtlil, node distance=5em, xshift=7.5em] {Passes};
- \node[process] (vlbe) [below of=rtlil, node distance=5em, xshift=-7.5em] {Verilog Backend};
- \node[process] (ilangbe) [below of=rtlil, node distance=5em, xshift=+7.5em] {ILANG Backend};
+ \node[process] (vlbe) [below of=rtlil, node distance=7em, xshift=-13em] {Verilog Backend};
+ \node[process] (ilangbe) [below of=rtlil, node distance=7em, xshift=0em] {ILANG Backend};
+ \node[process, dashed, fill=green!5] (otherbe) [below of=rtlil, node distance=7em, xshift=+13em] {Other Backends};
\draw[-latex] (vlog) -- (ast);
\draw[-latex] (vhdl) -- (ast);
\draw[latex-latex] (rtlil) -- (pass);
\draw[-latex] (rtlil) -- (vlbe);
\draw[-latex] (rtlil) -- (ilangbe);
+ \draw[-latex] (rtlil) -- (otherbe);
\end{tikzpicture}
\caption{Yosys simplified data flow (ellipses: data structures, rectangles: program modules)}
\label{fig:Overview_flow}
but keeps using yosys's internal gate library. This option is ignored if
the -script option is also used.
+ -lut <width>
+ generate netlist using luts of (max) the specified width.
+
-nocleanup
when this option is used, the temporary files created by this pass
are not removed. this is useful for debugging.
This is just a shortcut for 'select -clear'.
\end{lstlisting}
+\section{clean -- remove unused cells and wires}
+\label{cmd:clean}
+\begin{lstlisting}[numbers=left,frame=single]
+ clean [options] [selection]
+
+This is identical to 'opt_clean', but less verbose.
+
+When commands are seperated using the ';;' token, this command will be executed
+between the commands.
+
+When commands are seperated using the ';;;' token, this command will be executed
+in -purge mode between the commands.
+\end{lstlisting}
+
+\section{design -- save, restore and reset current design}
+\label{cmd:design}
+\begin{lstlisting}[numbers=left,frame=single]
+ design -reset
+
+Clear the current design.
+
+
+ design -save <name>
+
+Save the current design under the given name.
+
+
+ design -load <name>
+
+Reset the current design and load the design previously saved under the given
+name.
+\end{lstlisting}
+
\section{dfflibmap -- technology mapping of flip-flops}
\label{cmd:dfflibmap}
\begin{lstlisting}[numbers=left,frame=single]
pass is using the current design as mapping library.
\end{lstlisting}
+\section{freduce -- perform functional reduction}
+\label{cmd:freduce}
+\begin{lstlisting}[numbers=left,frame=single]
+ freduce [options] [selection]
+
+This pass performs functional reduction in the circuit. I.e. if two nodes are
+equivialent, they are merged to one node and one of the redundant drivers is
+removed.
+
+ -try
+ do not issue an error when the analysis fails.
+ (usually beacause of logic loops in the design)
+\end{lstlisting}
+
\section{fsm -- extract and optimize finite state machines}
\label{cmd:fsm}
\begin{lstlisting}[numbers=left,frame=single]
Load modules from a verilog file to the current design. A large subset of
Verilog-2005 is supported.
- -dump_ast
- dump abstract syntax tree (after simplification)
+ -dump_ast1
+ dump abstract syntax tree (before simplification)
- -dump_ast_diff
- dump ast differences before and after simplification
+ -dump_ast2
+ dump abstract syntax tree (after simplification)
-dump_vlog
dump ast as verilog code (after simplification)
-Dname[=definition]
define the preprocessor symbol 'name' and set its optional value
'definition'
+
+ -Idir
+ add 'dir' to the directories which are used when searching include
+ files
\end{lstlisting}
\section{rename -- rename object in the design}
Rename the specified object. Note that selection patterns are not supported
by this command.
+
+
+ rename -enumerate [selection]
+
+Assign short auto-generated names to all selected wires and cells with private
+names.
\end{lstlisting}
\section{sat -- solve a SAT problem in the circuit}
show the model for the specified signal. if no -show option is
passed then a set of signals to be shown is automatically selected.
+ -ignore_div_by_zero
+ ignore all solutions that involve a division by zero
+
The following options can be used to set up a sequential problem:
-seq <N>
scatter [selection]
This command adds additional intermediate nets on all cell ports. This is used
-for testing the correct use of the SigMap halper in passes. If you don't know
+for testing the correct use of the SigMap helper in passes. If you don't know
what this means: don't worry -- you only need this pass when testing your own
extensions to Yosys.
more than one library.
-prefix <prefix>
- generate <prefix>.dot and <prefix>.ps instead of ~/.yosys_show.{dot,ps}
+ generate <prefix>.* instead of ~/.yosys_show.*
-color <color> <wire>
assign the specified color to the specified wire. The object can be
transforms the internal RTL cells to the internal gate
library.
+ -opt
+ run 'opt' pass on all cells from map file before using them and run
+ 'opt_const' on all replacement cells before mapping recursively.
+
When a module in the map file has the 'celltype' attribute set, it will match
cells with a type that match the text value of this attribute.
low in order to explore more inner states in a state machine.
\end{lstlisting}
+\section{write\_edif -- write design to EDIF netlist file}
+\label{cmd:write_edif}
+\begin{lstlisting}[numbers=left,frame=single]
+ write_edif [options] [filename]
+
+Write the current design to an EDIF netlist file.
+
+ -top top_module
+ set the specified module as design top module
+\end{lstlisting}
+
\section{write\_ilang -- write design to ilang file}
\label{cmd:write_ilang}
\begin{lstlisting}[numbers=left,frame=single]
Write the current design to an 'ilang' file. (ilang is a text representation
of a design in yosys's internal format.)
+
+ -selected
+ only write selected parts of the design.
\end{lstlisting}
\section{write\_intersynth -- write design to InterSynth netlist file}
inputs or outputs. This option can be used multiple times to specify
more than one library.
+ -selected
+ only write selected modules. modules must be selected entirely or
+ not at all.
+
http://www.clifford.at/intersynth/
\end{lstlisting}
+\section{write\_spice -- write design to SPICE netlist file}
+\label{cmd:write_spice}
+\begin{lstlisting}[numbers=left,frame=single]
+ write_spice [options] [filename]
+
+Write the current design to an SPICE netlist file.
+
+ -big_endian
+ generate multi-bit ports in MSB first order
+ (default is LSB first)
+
+ -neg net_name
+ set the net name for constant 0 (default: Vss)
+
+ -pos net_name
+ set the net name for constant 1 (default: Vdd)
+
+ -nc_prefix
+ prefix for not-connected nets (default: _NC)
+
+ -top top_module
+ set the specified module as design top module
+\end{lstlisting}
+
\section{write\_verilog -- write design to verilog file}
\label{cmd:write_verilog}
\begin{lstlisting}[numbers=left,frame=single]
usually modules with the 'placeholder' attribute are ignored. with
this option set only the modules with the 'placeholder' attribute
are written to the output file.
+
+ -selected
+ only write selected modules. modules must be selected entirely or
+ not at all.
\end{lstlisting}
projects / yosys.git / commitdiff