from migen.genlib.resetsync import AsyncResetSynchronizer
from migen.genlib.record import *
from migen.genlib.fsm import FSM, NextState
-from migen.genlib.misc import chooser
+from migen.genlib.misc import chooser, FlipFlop, Counter, Timeout
from migen.flow.actor import *
from migen.flow.plumbing import Buffer
from migen.actorlib.structuring import Converter, Pipeline
mac_address=0x10e2d5000000,
ip_address="192.168.1.40"):
clk_freq = int((1/(platform.default_clk_period))*1000000000)
- self.submodules.uart2wb = LiteScopeUART2WB(platform.request("serial"), clk_freq, baud=115200)
+ self.submodules.uart2wb = LiteScopeUART2WB(platform.request("serial"), clk_freq, baudrate=115200)
SoC.__init__(self, platform, clk_freq, self.uart2wb,
with_cpu=False,
with_csr=True, csr_data_width=32,
return r
# Generic modules
-@DecorateModule(InsertReset)
-@DecorateModule(InsertCE)
-class FlipFlop(Module):
- def __init__(self, *args, **kwargs):
- self.d = Signal(*args, **kwargs)
- self.q = Signal(*args, **kwargs)
- self.sync += self.q.eq(self.d)
-
-@DecorateModule(InsertReset)
-@DecorateModule(InsertCE)
-class Counter(Module):
- def __init__(self, signal=None, **kwargs):
- if signal is None:
- self.value = Signal(**kwargs)
- else:
- self.value = signal
- self.width = flen(self.value)
- self.sync += self.value.eq(self.value+1)
-
-@DecorateModule(InsertReset)
-@DecorateModule(InsertCE)
-class Timeout(Module):
- def __init__(self, length):
- self.reached = Signal()
- ###
- value = Signal(max=length)
- self.sync += If(~self.reached, value.eq(value+1))
- self.comb += self.reached.eq(value == (length-1))
-
class BufferizeEndpoints(ModuleDecorator):
def __init__(self, submodule, *args):
ModuleDecorator.__init__(self, submodule)
from migen.genlib.resetsync import *
from migen.genlib.fsm import *
from migen.genlib.record import *
-from migen.genlib.misc import chooser, optree
+from migen.genlib.misc import chooser, optree, Counter, Timeout
from migen.genlib.cdc import *
from migen.flow.actor import *
from migen.flow.plumbing import Multiplexer, Demultiplexer
return n*logical_sector_size//4
# Generic modules
-@DecorateModule(InsertReset)
-@DecorateModule(InsertCE)
-class Counter(Module):
- def __init__(self, signal=None, **kwargs):
- if signal is None:
- self.value = Signal(**kwargs)
- else:
- self.value = signal
- self.width = flen(self.value)
- self.sync += self.value.eq(self.value+1)
-
-@DecorateModule(InsertReset)
-@DecorateModule(InsertCE)
-class Timeout(Module):
- def __init__(self, length):
- self.reached = Signal()
- ###
- value = Signal(max=length)
- self.sync += If(~self.reached, value.eq(value+1))
- self.comb += self.reached.eq(value == (length-1))
-
class BufferizeEndpoints(ModuleDecorator):
def __init__(self, submodule, *args):
ModuleDecorator.__init__(self, submodule)
csr_map.update(SoC.csr_map)
def __init__(self, platform):
clk_freq = 166*1000000
- self.submodules.uart2wb = LiteScopeUART2WB(platform.request("serial"), clk_freq, baud=115200)
+ self.submodules.uart2wb = LiteScopeUART2WB(platform.request("serial"), clk_freq, baudrate=115200)
SoC.__init__(self, platform, clk_freq, self.uart2wb,
with_cpu=False,
with_csr=True, csr_data_width=32,
source, sink = user_port.sink, user_port.source
- counter = Counter(bits_sign=32)
+ counter = Counter(32)
self.submodules += counter
scrambler = scrambler = InsertReset(Scrambler())
source, sink = user_port.sink, user_port.source
- counter = Counter(bits_sign=32)
- error_counter = Counter(self.errors, bits_sign=32)
+ counter = Counter(32)
+ error_counter = Counter(32)
self.submodules += counter, error_counter
+ self.comb += self.errors.eq(error_counter.value)
scrambler = InsertReset(Scrambler())
self.submodules += scrambler
]
self.fsm = fsm = FSM(reset_state="IDLE")
- loop_counter = Counter(bits_sign=8)
+ loop_counter = Counter(8)
self.submodules += fsm, loop_counter
fsm.act("IDLE",
self._done.status.eq(1),
)
)
- cycles_counter = Counter(self._cycles.status)
+ cycles_counter = Counter(32)
self.submodules += cycles_counter
self.sync += [
cycles_counter.reset.eq(start),
- cycles_counter.ce.eq(~fsm.ongoing("IDLE"))
+ cycles_counter.ce.eq(~fsm.ongoing("IDLE")),
+ self._cycles.status.eq(cycles_counter.value)
]
class LiteSATABISTIdentify(Module):
from migen.genlib.record import Record
from migen.flow.actor import Sink, Source
-from misoclib.com.uart import UARTRX, UARTTX
-
-class UART(Module, AutoCSR):
- def __init__(self, pads, clk_freq, baud=115200):
- self._tuning_word = CSRStorage(32, reset=int((baud/clk_freq)*2**32))
- tuning_word = self._tuning_word.storage
-
- ###
-
- self.rx = UARTRX(pads, tuning_word)
- self.tx = UARTTX(pads, tuning_word)
- self.submodules += self.rx, self.tx
+from misoclib.com.uart.phy.serial import UARTPHYSerial
class UARTPads:
def __init__(self):
"write" : 0x01,
"read" : 0x02
}
- def __init__(self, pads, clk_freq, baud=115200, share_uart=False):
+ def __init__(self, pads, clk_freq, baudrate=115200, share_uart=False):
self.wishbone = wishbone.Interface()
if share_uart:
self._sel = CSRStorage()
###
if share_uart:
- uart_mux = UARTMux(pads)
- uart = UART(uart_mux.bridge_pads, clk_freq, baud)
- self.submodules += uart_mux, uart
- self.shared_pads = uart_mux.shared_pads
- self.comb += uart_mux.sel.eq(self._sel.storage)
+ mux = UARTMux(pads)
+ uart = UARTPHYSerial(mux.bridge_pads, clk_freq, baudrate)
+ self.submodules += mux, uart
+ self.shared_pads = mux.shared_pads
+ self.comb += mux.sel.eq(self._sel.storage)
else:
- uart = UART(pads, clk_freq, baud)
+ uart = UARTPHYSerial(pads, clk_freq, baudrate)
self.submodules += uart
- byte_counter = Counter(bits_sign=3)
- word_counter = Counter(bits_sign=8)
+ byte_counter = Counter(3)
+ word_counter = Counter(8)
self.submodules += byte_counter, word_counter
cmd = Signal(8)
tx_data_ce = Signal()
self.sync += [
- If(cmd_ce, cmd.eq(uart.rx.source.d)),
- If(length_ce, length.eq(uart.rx.source.d)),
- If(address_ce, address.eq(Cat(uart.rx.source.d, address[0:24]))),
+ If(cmd_ce, cmd.eq(uart.source.d)),
+ If(length_ce, length.eq(uart.source.d)),
+ If(address_ce, address.eq(Cat(uart.source.d, address[0:24]))),
If(rx_data_ce,
- data.eq(Cat(uart.rx.source.d, data[0:24]))
+ data.eq(Cat(uart.source.d, data[0:24]))
).Elif(tx_data_ce,
data.eq(self.wishbone.dat_r)
)
]
fsm.act("IDLE",
timeout.reset.eq(1),
- If(uart.rx.source.stb,
+ If(uart.source.stb,
cmd_ce.eq(1),
- If( (uart.rx.source.d == self.cmds["write"]) |
- (uart.rx.source.d == self.cmds["read"]),
+ If( (uart.source.d == self.cmds["write"]) |
+ (uart.source.d == self.cmds["read"]),
NextState("RECEIVE_LENGTH")
),
byte_counter.reset.eq(1),
)
)
fsm.act("RECEIVE_LENGTH",
- If(uart.rx.source.stb,
+ If(uart.source.stb,
length_ce.eq(1),
NextState("RECEIVE_ADDRESS")
)
)
fsm.act("RECEIVE_ADDRESS",
- If(uart.rx.source.stb,
+ If(uart.source.stb,
address_ce.eq(1),
byte_counter.ce.eq(1),
If(byte_counter.value == 3,
)
)
fsm.act("RECEIVE_DATA",
- If(uart.rx.source.stb,
+ If(uart.source.stb,
rx_data_ce.eq(1),
byte_counter.ce.eq(1),
If(byte_counter.value == 3,
)
)
self.comb += \
- chooser(data, byte_counter.value, uart.tx.sink.d, n=4, reverse=True)
+ chooser(data, byte_counter.value, uart.sink.d, n=4, reverse=True)
fsm.act("SEND_DATA",
- uart.tx.sink.stb.eq(1),
- If(uart.tx.sink.ack,
+ uart.sink.stb.eq(1),
+ If(uart.sink.ack,
byte_counter.ce.eq(1),
If(byte_counter.value == 3,
word_counter.ce.eq(1),
from migen.bank.description import *
from migen.genlib.fsm import FSM, NextState
from migen.flow.actor import *
+from migen.genlib.misc import Counter, Timeout
from migen.actorlib.fifo import AsyncFIFO, SyncFIFO
from migen.flow.plumbing import Buffer
from migen.fhdl.specials import Memory
def hit_layout():
return [("hit", 1, DIR_M_TO_S)]
-
-@DecorateModule(InsertReset)
-@DecorateModule(InsertCE)
-class Counter(Module):
- def __init__(self, signal=None, **kwargs):
- if signal is None:
- self.value = Signal(**kwargs)
- else:
- self.value = signal
- self.width = flen(self.value)
- self.sync += self.value.eq(self.value+1)
-
-@DecorateModule(InsertReset)
-@DecorateModule(InsertCE)
-class Timeout(Module):
- def __init__(self, length):
- self.reached = Signal()
- ###
- value = Signal(max=length)
- self.sync += value.eq(value+1)
- self.comb += [
- self.reached.eq(value == length)
- ]
self.source = source = Source(data_layout(dw))
self.value = Signal(32)
###
- self.submodules.counter = Counter(bits_sign=32)
+ self.submodules.counter = Counter(32)
done = Signal()
self.comb += [
done.eq(self.counter.value >= self.value),
csr_map.update(SoC.csr_map)
def __init__(self, platform):
clk_freq = int((1/(platform.default_clk_period))*1000000000)
- self.submodules.uart2wb = LiteScopeUART2WB(platform.request("serial"), clk_freq, baud=115200)
+ self.submodules.uart2wb = LiteScopeUART2WB(platform.request("serial"), clk_freq, baudrate=115200)
SoC.__init__(self, platform, clk_freq, self.uart2wb,
with_cpu=False,
with_csr=True, csr_data_width=32,
except:
pass
- self.submodules.counter0 = counter0 = Counter(bits_sign=8)
- self.submodules.counter1 = counter1 = Counter(bits_sign=8)
+ self.submodules.counter0 = counter0 = Counter(8)
+ self.submodules.counter1 = counter1 = Counter(8)
self.comb += [
counter0.ce.eq(1),
If(counter0.value == 16,
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